From 0c9a7817b65cb0daef8631a11eaaad50838acd5a Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Thu, 30 Jul 2015 16:30:00 -0700
Subject: [PATCH] Reduce outstanding mem accesses for FPGAConfig (to reduce
 MIFTagBits < 7)

---
 src/main/scala/Configs.scala | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 8dc7a5ca..a71def02 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -229,6 +229,7 @@ class ZscaleConfig extends ChiselConfig(new WithZscale ++ new DefaultConfig)
 
 class FPGAConfig extends ChiselConfig (
   (pname,site,here) => pname match {
+    case NAcquireTransactors => 4
     case UseBackupMemoryPort => false
   }
 )