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Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7)

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Henry Cook 2015-07-30 16:30:00 -07:00
parent 51c42083d0
commit 0c9a7817b6
1 changed files with 1 additions and 0 deletions
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src/main/scala/Configs.scala
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@ -229,6 +229,7 @@ class ZscaleConfig extends ChiselConfig(new WithZscale ++ new DefaultConfig)
class FPGAConfig extends ChiselConfig ( class FPGAConfig extends ChiselConfig (
(pname,site,here) => pname match { (pname,site,here) => pname match {
case NAcquireTransactors => 4
case UseBackupMemoryPort => false case UseBackupMemoryPort => false
} }
) )