riscv/rocket-chip
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refactor I$ config into RocketConfiguration

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Andrew Waterman committed 2012-11-04 17:00:19 -08:00
1 parent 4ed2d614a2
commit 0c372fc9ec
2 files changed
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riscv-rocket
+1 -1
Submodule riscv-rocket updated: 17301fbfbd...45d639ef57.
src/main/scala/RocketChip.scala
+2 -1
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@@ -207,7 +207,8 @@ class Top extends Component {
val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
implicit val rconf = RocketConfiguration(NTILES, co)
val ic = ICacheConfig(128, 2, co)
implicit val rconf = RocketConfiguration(NTILES, co, ic)
val tile = new Tile(resetSignal = hl.reset)
tile.io.host.reset := Reg(Reg(hl.reset))