From 0c372fc9ec6de5aaa9248ba90dbfdc774ed541b2 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 4 Nov 2012 17:00:19 -0800 Subject: [PATCH] refactor I$ config into RocketConfiguration --- riscv-rocket | 2 +- src/main/scala/RocketChip.scala | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/riscv-rocket b/riscv-rocket index 17301fbf..45d639ef 160000 --- a/riscv-rocket +++ b/riscv-rocket @@ -1 +1 @@ -Subproject commit 17301fbfbd10034c61f12663d53599a8de7d00ce +Subproject commit 45d639ef571e0ba5a48c59b014d58e3de00270b2 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 14eb9fa8..dd4a6e2d 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -207,7 +207,8 @@ class Top extends Component { val hl = uncore.io.htif(i) val tl = uncore.io.tiles(i) - implicit val rconf = RocketConfiguration(NTILES, co) + val ic = ICacheConfig(128, 2, co) + implicit val rconf = RocketConfiguration(NTILES, co, ic) val tile = new Tile(resetSignal = hl.reset) tile.io.host.reset := Reg(Reg(hl.reset))