riscv/rocket-chip
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Merge branch 'master' into rocc-fpu-port

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This commit is contained in:
Howard Mao 2015-12-01 18:00:28 -08:00
commit 08f77ca90d
1 changed files with 11 additions and 10 deletions
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21
rocket/src/main/scala/tile.scala
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@ -8,16 +8,16 @@ import Util._
import cde.{Parameters, Field} import cde.{Parameters, Field}
case object CoreName extends Field[String] case object CoreName extends Field[String]
case object BuildRoCC extends Field[Seq[Parameters => RoCC]] case object BuildRoCC extends Field[Seq[RoccParameters]]
case object RoccOpcodes extends Field[Seq[OpcodeSet]]
case object RoccAcceleratorMemChannels extends Field[Seq[Int]] case class RoccParameters(
case object RoccUseFPU extends Field[Seq[Boolean]] opcodes: OpcodeSet,
generator: Parameters => RoCC,
nMemChannels: Int = 1)
abstract class Tile(resetSignal: Bool = null) abstract class Tile(resetSignal: Bool = null)
(implicit p: Parameters) extends Module(_reset = resetSignal) { (implicit p: Parameters) extends Module(_reset = resetSignal) {
val buildRocc = p(BuildRoCC) val buildRocc = p(BuildRoCC)
val roccOpcodes = p(RoccOpcodes)
val roccMemChannels = p(RoccAcceleratorMemChannels)
val usingRocc = !buildRocc.isEmpty val usingRocc = !buildRocc.isEmpty
val nRocc = buildRocc.size val nRocc = buildRocc.size
val roccUseFPU = p(RoccUseFPU) val roccUseFPU = p(RoccUseFPU)
@ -69,13 +69,14 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
val respArb = Module(new RRArbiter(new RoCCResponse, nRocc)) val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
core.io.rocc.resp <> respArb.io.out core.io.rocc.resp <> respArb.io.out
val roccOpcodes = buildRocc.map(_.opcodes)
val cmdRouter = Module(new RoccCommandRouter(roccOpcodes)) val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
cmdRouter.io.in <> core.io.rocc.cmd cmdRouter.io.in <> core.io.rocc.cmd
val roccs = buildRocc.zip(roccMemChannels).zipWithIndex.map { val roccs = buildRocc.zipWithIndex.map {
case ((buildItHere, nchannels), i) => case (RoccParameters(_, generator, nchannels), i) =>
val accelParams = p.alterPartial({ case RoccNMemChannels => nchannels}) val accelParams = p.alterPartial({ case RoccNMemChannels => nchannels })
val rocc = buildItHere(accelParams) val rocc = generator(accelParams)
val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams)) val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
rocc.io.cmd <> cmdRouter.io.out(i) rocc.io.cmd <> cmdRouter.io.out(i)
rocc.io.s := core.io.rocc.s rocc.io.s := core.io.rocc.s