From e76dfa55f76610811469a82d369aa46873bff25c Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 1 Dec 2015 17:54:56 -0800
Subject: [PATCH] change the way rocc is parameterized

---
 rocket/src/main/scala/tile.scala | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 7c838475..c92de644 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -8,15 +8,16 @@ import Util._
 import cde.{Parameters, Field}
 
 case object CoreName extends Field[String]
-case object BuildRoCC extends Field[Seq[Parameters => RoCC]]
-case object RoccOpcodes extends Field[Seq[OpcodeSet]]
-case object RoccAcceleratorMemChannels extends Field[Seq[Int]]
+case object BuildRoCC extends Field[Seq[RoccParameters]]
+
+case class RoccParameters(
+  opcodes: OpcodeSet,
+  generator: Parameters => RoCC,
+  nMemChannels: Int = 1)
 
 abstract class Tile(resetSignal: Bool = null)
                    (implicit p: Parameters) extends Module(_reset = resetSignal) {
   val buildRocc = p(BuildRoCC)
-  val roccOpcodes = p(RoccOpcodes)
-  val roccMemChannels = p(RoccAcceleratorMemChannels)
   val usingRocc = !buildRocc.isEmpty
   val nRocc = buildRocc.size
   val nDCachePorts = 2 + nRocc
@@ -66,13 +67,14 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
     val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
     core.io.rocc.resp <> respArb.io.out
 
+    val roccOpcodes = buildRocc.map(_.opcodes)
     val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
     cmdRouter.io.in <> core.io.rocc.cmd
 
-    val roccs = buildRocc.zip(roccMemChannels).zipWithIndex.map {
-      case ((buildItHere, nchannels), i) =>
-        val accelParams = p.alterPartial({ case RoccNMemChannels => nchannels})
-        val rocc = buildItHere(accelParams)
+    val roccs = buildRocc.zipWithIndex.map {
+      case (RoccParameters(_, generator, nchannels), i) =>
+        val accelParams = p.alterPartial({ case RoccNMemChannels => nchannels })
+        val rocc = generator(accelParams)
         val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
         rocc.io.cmd <> cmdRouter.io.out(i)
         rocc.io.s := core.io.rocc.s