riscv/rocket-chip
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Remove most of mstatus when user mode isn't supported

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This commit is contained in:
Andrew Waterman 2016-05-25 15:37:32 -07:00
parent 5442b89664
commit 00ea9a7d82
2 changed files with 10 additions and 2 deletions
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10
rocket/src/main/scala/csr.scala
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@ -363,7 +363,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
reg_mstatus.prv := reg_mstatus.spp reg_mstatus.prv := reg_mstatus.spp
}.otherwise { }.otherwise {
when (reg_mstatus.mpp(1)) { reg_mstatus.mie := reg_mstatus.mpie } when (reg_mstatus.mpp(1)) { reg_mstatus.mie := reg_mstatus.mpie }
when (reg_mstatus.mpp(0)) { reg_mstatus.sie := reg_mstatus.mpie } .elsewhen (Bool(usingVM) && reg_mstatus.mpp(0)) { reg_mstatus.sie := reg_mstatus.mpie }
reg_mstatus.mpie := false reg_mstatus.mpie := false
reg_mstatus.mpp := PRV.U reg_mstatus.mpp := PRV.U
reg_mstatus.prv := reg_mstatus.mpp reg_mstatus.prv := reg_mstatus.mpp
@ -388,7 +388,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
reg_mstatus.mie := new_mstatus.mie reg_mstatus.mie := new_mstatus.mie
reg_mstatus.mpie := new_mstatus.mpie reg_mstatus.mpie := new_mstatus.mpie
val supportedModes = Vec((PRV.M :: PRV.U :: (if (usingVM) List(PRV.S) else Nil)).map(UInt(_))) val supportedModes = Vec((PRV.M +: (if (usingUser) Some(PRV.U) else None) ++: (if (usingVM) Seq(PRV.S) else Nil)).map(UInt(_)))
if (supportedModes.size > 1) { if (supportedModes.size > 1) {
reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mprv := new_mstatus.mprv
when (supportedModes contains new_mstatus.mpp) { reg_mstatus.mpp := new_mstatus.mpp } when (supportedModes contains new_mstatus.mpp) { reg_mstatus.mpp := new_mstatus.mpp }
@ -459,4 +459,10 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
io.rocc.csr.waddr := io.rw.addr io.rocc.csr.waddr := io.rw.addr
io.rocc.csr.wdata := wdata io.rocc.csr.wdata := wdata
io.rocc.csr.wen := wen io.rocc.csr.wen := wen
if (!usingUser) {
reg_mstatus.mpp := PRV.M
reg_mstatus.prv := PRV.M
reg_mstatus.mprv := false
}
} }

2
rocket/src/main/scala/rocket.scala
View File

@ -14,6 +14,7 @@ case object XLen extends Field[Int]
case object FetchWidth extends Field[Int] case object FetchWidth extends Field[Int]
case object RetireWidth extends Field[Int] case object RetireWidth extends Field[Int]
case object UseVM extends Field[Boolean] case object UseVM extends Field[Boolean]
case object UseUser extends Field[Boolean]
case object UseAtomics extends Field[Boolean] case object UseAtomics extends Field[Boolean]
case object UsePerfCounters extends Field[Boolean] case object UsePerfCounters extends Field[Boolean]
case object FastLoadWord extends Field[Boolean] case object FastLoadWord extends Field[Boolean]
@ -32,6 +33,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
val xLen = p(XLen) val xLen = p(XLen)
val usingVM = p(UseVM) val usingVM = p(UseVM)
val usingUser = p(UseUser)
val usingFPU = p(UseFPU) val usingFPU = p(UseFPU)
val usingAtomics = p(UseAtomics) val usingAtomics = p(UseAtomics)
val usingFDivSqrt = p(FDivSqrt) val usingFDivSqrt = p(FDivSqrt)