From 00ea9a7d829119368842f33394f4d3c686308862 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 25 May 2016 15:37:32 -0700 Subject: [PATCH] Remove most of mstatus when user mode isn't supported --- rocket/src/main/scala/csr.scala | 10 ++++++++-- rocket/src/main/scala/rocket.scala | 2 ++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala index 0ccce9aa..aa1ea014 100644 --- a/rocket/src/main/scala/csr.scala +++ b/rocket/src/main/scala/csr.scala @@ -363,7 +363,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) reg_mstatus.prv := reg_mstatus.spp }.otherwise { when (reg_mstatus.mpp(1)) { reg_mstatus.mie := reg_mstatus.mpie } - when (reg_mstatus.mpp(0)) { reg_mstatus.sie := reg_mstatus.mpie } + .elsewhen (Bool(usingVM) && reg_mstatus.mpp(0)) { reg_mstatus.sie := reg_mstatus.mpie } reg_mstatus.mpie := false reg_mstatus.mpp := PRV.U reg_mstatus.prv := reg_mstatus.mpp @@ -388,7 +388,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie - val supportedModes = Vec((PRV.M :: PRV.U :: (if (usingVM) List(PRV.S) else Nil)).map(UInt(_))) + val supportedModes = Vec((PRV.M +: (if (usingUser) Some(PRV.U) else None) ++: (if (usingVM) Seq(PRV.S) else Nil)).map(UInt(_))) if (supportedModes.size > 1) { reg_mstatus.mprv := new_mstatus.mprv when (supportedModes contains new_mstatus.mpp) { reg_mstatus.mpp := new_mstatus.mpp } @@ -459,4 +459,10 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) io.rocc.csr.waddr := io.rw.addr io.rocc.csr.wdata := wdata io.rocc.csr.wen := wen + + if (!usingUser) { + reg_mstatus.mpp := PRV.M + reg_mstatus.prv := PRV.M + reg_mstatus.mprv := false + } } diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala index 24f62814..823d0c09 100644 --- a/rocket/src/main/scala/rocket.scala +++ b/rocket/src/main/scala/rocket.scala @@ -14,6 +14,7 @@ case object XLen extends Field[Int] case object FetchWidth extends Field[Int] case object RetireWidth extends Field[Int] case object UseVM extends Field[Boolean] +case object UseUser extends Field[Boolean] case object UseAtomics extends Field[Boolean] case object UsePerfCounters extends Field[Boolean] case object FastLoadWord extends Field[Boolean] @@ -32,6 +33,7 @@ trait HasCoreParameters extends HasAddrMapParameters { val xLen = p(XLen) val usingVM = p(UseVM) + val usingUser = p(UseUser) val usingFPU = p(UseFPU) val usingAtomics = p(UseAtomics) val usingFDivSqrt = p(FDivSqrt)