riscv/rocket-chip
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Remove most of mstatus when user mode isn't supported

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Andrew Waterman committed 2016-05-25 15:37:32 -07:00
1 parent 5442b89664
commit 00ea9a7d82
2 files changed
+10 -2
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rocket/src/main/scala/rocket.scala
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@@ -14,6 +14,7 @@ case object XLen extends Field[Int]
case object FetchWidth extends Field[Int]
case object RetireWidth extends Field[Int]
case object UseVM extends Field[Boolean]
case object UseUser extends Field[Boolean]
case object UseAtomics extends Field[Boolean]
case object UsePerfCounters extends Field[Boolean]
case object FastLoadWord extends Field[Boolean]
@@ -32,6 +33,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
val xLen = p(XLen)
val usingVM = p(UseVM)
val usingUser = p(UseUser)
val usingFPU = p(UseFPU)
val usingAtomics = p(UseAtomics)
val usingFDivSqrt = p(FDivSqrt)