riscv/rocket-chip
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Don't ignore data value when writing MIPI

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This commit is contained in:
Andrew Waterman 2016-01-12 16:23:06 -08:00
parent 7bf503a275
commit 00d17abd78
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/csr.scala
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@ -398,7 +398,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
reg_mip.msip := new_mip.msip reg_mip.msip := new_mip.msip
} }
when (decoded_addr(CSRs.mipi)) { when (decoded_addr(CSRs.mipi)) {
reg_mip.msip := true reg_mip.msip := wdata(0)
} }
when (decoded_addr(CSRs.mie)) { when (decoded_addr(CSRs.mie)) {
val new_mie = new MIP().fromBits(wdata) val new_mie = new MIP().fromBits(wdata)