diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index c9675527..1c29a2ef 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -398,7 +398,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
       reg_mip.msip := new_mip.msip
     }
     when (decoded_addr(CSRs.mipi)) {
-      reg_mip.msip := true
+      reg_mip.msip := wdata(0)
     }
     when (decoded_addr(CSRs.mie)) {
       val new_mie = new MIP().fromBits(wdata)