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rocket-chip/rocket/src/main/scala/queues.scala

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Scala
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package Top
import Chisel._
import Node._;
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class ioQueue[T <: Data](flushable: Boolean)(data: => T) extends Bundle
{
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val flush = if (flushable) Bool(INPUT) else null
val enq = new ioDecoupled()(data)
val deq = new ioDecoupled()(data).flip
}
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class queue[T <: Data](entries: Int, flushable: Boolean = false)(data: => T) extends Component
{
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val io = new ioQueue(flushable)(data)
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val enq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
val deq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
val maybe_full = Reg(resetVal = Bool(false))
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io.deq.valid := maybe_full || enq_ptr != deq_ptr
io.enq.ready := !maybe_full || enq_ptr != deq_ptr
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val do_enq = io.enq.ready && io.enq.valid
val do_deq = io.deq.ready && io.deq.valid
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if (flushable) {
when (io.flush) {
deq_ptr <== UFix(0)
enq_ptr <== UFix(0)
maybe_full <== Bool(false)
}
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}
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when (do_deq) {
deq_ptr <== deq_ptr + UFix(1)
}
when (do_enq) {
enq_ptr <== enq_ptr + UFix(1)
}
when (do_enq != do_deq) {
maybe_full <== do_enq
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}
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Mem(entries, do_enq, enq_ptr, io.enq.bits).read(deq_ptr) <> io.deq.bits
}