46 lines
1.1 KiB
Scala
46 lines
1.1 KiB
Scala
package Top
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import Chisel._
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import Node._;
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class ioQueue[T <: Data](flushable: Boolean)(data: => T) extends Bundle
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{
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val flush = if (flushable) Bool(INPUT) else null
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val enq = new ioDecoupled()(data)
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val deq = new ioDecoupled()(data).flip
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}
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class queue[T <: Data](entries: Int, flushable: Boolean = false)(data: => T) extends Component
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{
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val io = new ioQueue(flushable)(data)
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val enq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
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val deq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
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val maybe_full = Reg(resetVal = Bool(false))
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io.deq.valid := maybe_full || enq_ptr != deq_ptr
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io.enq.ready := !maybe_full || enq_ptr != deq_ptr
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val do_enq = io.enq.ready && io.enq.valid
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val do_deq = io.deq.ready && io.deq.valid
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if (flushable) {
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when (io.flush) {
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deq_ptr <== UFix(0)
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enq_ptr <== UFix(0)
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maybe_full <== Bool(false)
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}
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}
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when (do_deq) {
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deq_ptr <== deq_ptr + UFix(1)
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}
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when (do_enq) {
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enq_ptr <== enq_ptr + UFix(1)
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}
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when (do_enq != do_deq) {
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maybe_full <== do_enq
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}
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Mem(entries, do_enq, enq_ptr, io.enq.bits).read(deq_ptr) <> io.deq.bits
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}
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