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rocket-chip/rocket/src/main/scala/dcache.scala

360 lines
13 KiB
Scala
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package Top {
import Chisel._
import Node._;
import Constants._;
import scala.math._;
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// interface between D$ and processor pipeline
class ioDmem(view: List[String] = null) extends Bundle(view) {
val req_val = Bool('input);
val req_rdy = Bool('output);
val req_cmd = Bits(4, 'input);
val req_type = Bits(3, 'input);
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val req_addr = UFix(PADDR_BITS, 'input);
val req_data = Bits(64, 'input);
val req_tag = Bits(5, 'input);
val resp_miss = Bool('output);
val resp_val = Bool('output);
val resp_data = Bits(64, 'output);
val resp_tag = Bits(12, 'output);
}
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// interface between D$ and next level in memory hierarchy
class ioDcache(view: List[String] = null) extends Bundle(view) {
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val req_addr = UFix(PADDR_BITS, 'input);
val req_tag = UFix(3, 'input);
val req_val = Bool('input);
val req_rdy = Bool('output);
val req_wdata = Bits(128, 'input);
val req_rw = Bool('input);
val resp_data = Bits(128, 'output);
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// val resp_tag = Bits(3, 'output);
val resp_val = Bool('output);
}
class ioDCacheDM extends Bundle() {
val cpu = new ioDmem();
val mem = new ioDcache().flip();
}
// state machine to flush (write back dirty lines, invalidate clean ones) the D$
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class rocketDCacheDM_flush(lines: Int) extends Component {
val io = new ioDCacheDM();
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val dcache = new rocketDCacheDM(lines);
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val addrbits = PADDR_BITS;
val indexbits = ceil(log10(lines)/log10(2)).toInt;
val offsetbits = 6;
val tagmsb = addrbits - 1;
val taglsb = indexbits+offsetbits;
val indexmsb = taglsb-1;
val indexlsb = offsetbits;
val offsetmsb = indexlsb-1;
val offsetlsb = 3;
val flush_count = Reg(resetVal = UFix(0, indexbits));
val flush_resp_count = Reg(resetVal = UFix(0, indexbits));
val flushing = Reg(resetVal = Bool(false));
val flush_waiting = Reg(resetVal = Bool(false));
val r_cpu_req_tag = Reg(resetVal = Bits(0, 5));
when (io.cpu.req_val && io.cpu.req_rdy && (io.cpu.req_cmd === M_FLA))
{
r_cpu_req_tag <== io.cpu.req_tag;
flushing <== Bool(true);
flush_waiting <== Bool(true);
}
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when (dcache.io.cpu.req_rdy && (flush_count === ~Bits(0, indexbits))) {
flushing <== Bool(false);
}
when (dcache.io.cpu.resp_val && (dcache.io.cpu.resp_tag === r_cpu_req_tag) && (flush_resp_count === ~Bits(0, indexbits))) {
flush_waiting <== Bool(false);
}
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when (flushing && dcache.io.cpu.req_rdy) {
flush_count <== flush_count + UFix(1,1);
}
when (flush_waiting && dcache.io.cpu.resp_val && (dcache.io.cpu.resp_tag(5,0) === r_cpu_req_tag)) {
flush_resp_count <== flush_resp_count + UFix(1,1);
}
dcache.io.cpu.req_val := (io.cpu.req_val && (io.cpu.req_cmd != M_FLA) && !flush_waiting) || flushing;
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dcache.io.cpu.req_cmd := Mux(flushing, M_FLA, io.cpu.req_cmd);
dcache.io.cpu.req_addr := Mux(flushing, Cat(Bits(0,tagmsb-taglsb+1), flush_count, Bits(0,offsetbits)).toUFix, io.cpu.req_addr);
dcache.io.cpu.req_tag := Mux(flushing, r_cpu_req_tag, io.cpu.req_tag);
dcache.io.cpu.req_type := io.cpu.req_type;
dcache.io.cpu.req_data ^^ io.cpu.req_data;
dcache.io.mem ^^ io.mem;
io.cpu.req_rdy := dcache.io.cpu.req_rdy && !flush_waiting;
io.cpu.resp_miss := dcache.io.cpu.resp_miss;
io.cpu.resp_data := dcache.io.cpu.resp_data;
io.cpu.resp_tag := dcache.io.cpu.resp_tag;
io.cpu.resp_val := dcache.io.cpu.resp_val &
!(flush_waiting && (io.cpu.resp_tag === r_cpu_req_tag) && (flush_count != ~Bits(0, addrbits)));
}
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class rocketDCacheDM(lines: Int) extends Component {
val io = new ioDCacheDM();
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val addrbits = PADDR_BITS;
val indexbits = ceil(log10(lines)/log10(2)).toInt;
val offsetbits = 6;
val tagmsb = addrbits - 1;
val taglsb = indexbits+offsetbits;
val indexmsb = taglsb-1;
val indexlsb = offsetbits;
val offsetmsb = indexlsb-1;
val offsetlsb = 3;
val s_reset :: s_ready :: s_replay_load :: s_start_writeback :: s_writeback :: s_req_refill :: s_refill :: s_resolve_miss :: Nil = Enum(8) { UFix() };
val state = Reg(resetVal = s_reset);
val r_cpu_req_addr = Reg(resetVal = Bits(0, addrbits));
val r_cpu_req_val = Reg(resetVal = Bool(false));
val r_cpu_req_cmd = Reg(resetVal = Bits(0,4));
val r_cpu_req_type = Reg(resetVal = Bits(0,3));
val r_cpu_req_tag = Reg(resetVal = Bits(0,5));
val p_store_data = Reg(resetVal = Bits(0,64));
val p_store_addr = Reg(resetVal = Bits(0,64));
val p_store_cmd = Reg(resetVal = Bits(0,4));
val p_store_type = Reg(resetVal = Bits(0,3));
val p_store_valid = Reg(resetVal = Bool(false));
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val req_load = (r_cpu_req_cmd === M_XRD) || (r_cpu_req_cmd === M_PRD);
val req_store = (r_cpu_req_cmd === M_XWR);
val req_flush = (r_cpu_req_cmd === M_FLA);
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val req_ptw_load = (r_cpu_req_cmd === M_PRD);
when (io.cpu.req_val && io.cpu.req_rdy) {
r_cpu_req_addr <== io.cpu.req_addr;
r_cpu_req_cmd <== io.cpu.req_cmd;
r_cpu_req_type <== io.cpu.req_type;
r_cpu_req_tag <== io.cpu.req_tag;
}
when (io.cpu.req_val && io.cpu.req_rdy && (io.cpu.req_cmd === M_XWR)) {
p_store_data <== io.cpu.req_data;
p_store_addr <== io.cpu.req_addr;
p_store_type <== io.cpu.req_type;
p_store_valid <== Bool(true);
}
when (io.cpu.req_rdy) {
r_cpu_req_val <== io.cpu.req_val;
}
when ((state === s_resolve_miss) && !req_load) {
r_cpu_req_val <== Bool(false);
}
// counter
val rr_count = Reg(resetVal = UFix(0,2));
val rr_count_next = rr_count + UFix(1);
when (((state === s_refill) && io.mem.resp_val) || ((state === s_writeback) && io.mem.req_rdy)) {
rr_count <== rr_count_next;
}
// tag array
val tagbits = addrbits-(indexbits+offsetbits);
val tag_we =
((state === s_refill) && io.mem.req_rdy && (rr_count === UFix(3,2))) ||
((state === s_resolve_miss) && req_flush);
val tag_array = new rocketSRAMsp(lines, tagbits);
val tag_raddr =
Mux((state === s_ready), io.cpu.req_addr(indexmsb, indexlsb).toUFix,
r_cpu_req_addr(indexmsb, indexlsb).toUFix);
tag_array.io.a := tag_raddr;
tag_array.io.d := r_cpu_req_addr(tagmsb, taglsb);
tag_array.io.we := tag_we;
tag_array.io.bweb := ~Bits(0,tagbits);
tag_array.io.ce := Bool(true); // FIXME
val tag_rdata = tag_array.io.q;
// valid bit array
val vb_array = Reg(resetVal = Bits(0, lines));
val vb_rdata = Reg(vb_array(tag_raddr));
when (tag_we && !req_flush) {
vb_array <== vb_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(1,1));
}
when (tag_we && req_flush) {
vb_array <== vb_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(0,1));
}
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val tag_valid = vb_rdata.toBool;
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val tag_match = tag_valid && (tag_rdata === r_cpu_req_addr(tagmsb, taglsb));
// generate write mask and store data signals based on store type and address LSBs
val wmask_b =
Mux(p_store_addr(2,0) === UFix(0, 3), Bits("b0000_0001", 8),
Mux(p_store_addr(2,0) === UFix(1, 3), Bits("b0000_0010", 8),
Mux(p_store_addr(2,0) === UFix(2, 3), Bits("b0000_0100", 8),
Mux(p_store_addr(2,0) === UFix(3, 3), Bits("b0000_1000", 8),
Mux(p_store_addr(2,0) === UFix(4, 3), Bits("b0001_0000", 8),
Mux(p_store_addr(2,0) === UFix(5, 3), Bits("b0010_0000", 8),
Mux(p_store_addr(2,0) === UFix(6, 3), Bits("b0100_0000", 8),
Mux(p_store_addr(2,0) === UFix(7, 3), Bits("b1000_0000", 8),
UFix(0, 8)))))))));
val wmask_h =
Mux(p_store_addr(2,1) === UFix(0, 2), Bits("b0000_0011", 8),
Mux(p_store_addr(2,1) === UFix(1, 2), Bits("b0000_1100", 8),
Mux(p_store_addr(2,1) === UFix(2, 2), Bits("b0011_0000", 8),
Mux(p_store_addr(2,1) === UFix(3, 2), Bits("b1100_0000", 8),
UFix(0, 8)))));
val wmask_w =
Mux(p_store_addr(2) === UFix(0, 1), Bits("b0000_1111", 8),
Mux(p_store_addr(2) === UFix(1, 1), Bits("b1111_0000", 8),
UFix(0, 8)));
val wmask_d =
Bits("b1111_1111", 8);
val store_wmask =
Mux(p_store_type === MT_B, wmask_b,
Mux(p_store_type === MT_H, wmask_h,
Mux(p_store_type === MT_W, wmask_w,
Mux(p_store_type === MT_D, wmask_d,
UFix(0, 8)))));
val store_data =
Mux(p_store_type === MT_B, Fill(8, p_store_data( 7,0)),
Mux(p_store_type === MT_H, Fill(4, p_store_data(15,0)),
Mux(p_store_type === MT_W, Fill(2, p_store_data(31,0)),
Mux(p_store_type === MT_D, p_store_data,
UFix(0, 64)))));
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val addr_match = (r_cpu_req_addr(tagmsb, offsetlsb) === p_store_addr(tagmsb, offsetlsb));
val ldst_conflict = r_cpu_req_val && req_load && p_store_valid && addr_match;
val drain_store =
(state === s_ready) && p_store_valid &&
(!(io.cpu.req_val && (io.cpu.req_cmd === M_XRD)) ||
r_cpu_req_val && req_load && p_store_valid && addr_match);
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val resolve_store = (state === s_resolve_miss) && req_store;
val do_store = drain_store | resolve_store;
// dirty bit array
val db_array = Reg(resetVal = Bits(0, lines));
val db_rdata = Reg(db_array(tag_raddr));
val tag_dirty = db_rdata.toBool;
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when (do_store) {
p_store_valid <== Bool(false);
db_array <== db_array.bitSet(p_store_addr(indexmsb, indexlsb).toUFix, UFix(1,1));
}
when (tag_we) {
db_array <== db_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(0,1));
}
// data array
val data_array = new rocketSRAMsp(lines*4, 128);
val store_wmask_expand =
Cat(Fill(8, store_wmask(7)),
Fill(8, store_wmask(6)),
Fill(8, store_wmask(5)),
Fill(8, store_wmask(4)),
Fill(8, store_wmask(3)),
Fill(8, store_wmask(2)),
Fill(8, store_wmask(1)),
Fill(8, store_wmask(0)));
val da_store_wmask =
Mux(p_store_addr(offsetlsb).toBool,
Cat(store_wmask_expand, Bits(0,64)),
Cat(Bits(0,64), store_wmask_expand));
data_array.io.a :=
Mux(do_store, p_store_addr(indexmsb, offsetmsb-1),
Mux((state === s_writeback) && io.mem.req_rdy, Cat(r_cpu_req_addr(indexmsb, indexlsb), rr_count_next),
Mux((state === s_start_writeback) || (state === s_writeback) || (state === s_refill), Cat(r_cpu_req_addr(indexmsb, indexlsb), rr_count),
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Mux((state === s_resolve_miss) || (state === s_replay_load), r_cpu_req_addr(indexmsb, offsetmsb-1),
io.cpu.req_addr(indexmsb, offsetmsb-1))))).toUFix;
data_array.io.d :=
Mux((state === s_refill), io.mem.resp_data,
Cat(store_data, store_data));
data_array.io.we := ((state === s_refill) && io.mem.resp_val) || do_store;
data_array.io.bweb :=
Mux((state === s_refill), ~Bits(0,128),
da_store_wmask);
data_array.io.ce := Bool(true); // FIXME
val data_array_rdata = data_array.io.q;
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val miss = (state === s_ready) && r_cpu_req_val && req_load && (!tag_match || (p_store_valid && addr_match));
// output signals
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io.cpu.req_rdy := (state === s_ready) && !ldst_conflict && (!r_cpu_req_val || (tag_match && !req_flush));
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io.cpu.resp_val := ((state === s_ready) && r_cpu_req_val && tag_match && req_load && !(p_store_valid && addr_match)) ||
((state === s_resolve_miss) && req_flush);
io.cpu.resp_miss := miss;
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// io.cpu.resp_tag := Cat(Bits(0,1), r_cpu_req_type, r_cpu_req_addr(2,0), r_cpu_req_tag);
io.cpu.resp_tag := Cat(req_ptw_load, r_cpu_req_type, r_cpu_req_addr(2,0), r_cpu_req_tag);
io.cpu.resp_data :=
Mux(r_cpu_req_addr(offsetlsb).toBool, data_array_rdata(127, 64),
data_array_rdata(63,0));
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io.mem.req_val := (state === s_req_refill) || (state === s_writeback);
io.mem.req_rw := (state === s_writeback);
io.mem.req_wdata := data_array_rdata;
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io.mem.req_tag := UFix(0);
io.mem.req_addr :=
Mux(state === s_writeback, Cat(tag_rdata, r_cpu_req_addr(indexmsb, indexlsb), rr_count).toUFix,
Cat(r_cpu_req_addr(tagmsb, indexlsb), Bits(0,2)).toUFix);
// control state machine
switch (state) {
is (s_reset) {
state <== s_ready;
}
is (s_ready) {
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when (ldst_conflict) {
state <== s_replay_load;
}
when (!r_cpu_req_val || tag_match) {
state <== s_ready;
}
when (tag_valid & tag_dirty) {
state <== s_start_writeback;
}
when (req_flush) {
state <== s_resolve_miss;
}
otherwise {
state <== s_req_refill;
}
}
is (s_replay_load) {
state <== s_ready;
}
is (s_start_writeback) {
state <== s_writeback;
}
is (s_writeback) {
when (io.mem.req_rdy && (rr_count === UFix(3,2))) {
when (req_flush) { state <== s_resolve_miss; }
otherwise { state <== s_req_refill; }
}
}
is (s_req_refill)
{
when (io.mem.req_rdy) { state <== s_refill; }
}
is (s_refill) {
when (io.mem.resp_val && (rr_count === UFix(3,2))) { state <== s_resolve_miss; }
}
is (s_resolve_miss) {
state <== s_ready;
}
}
}
}