252 lines
9.9 KiB
Scala
252 lines
9.9 KiB
Scala
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package Top {
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import Chisel._
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import Node._;
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import Constants._;
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import scala.math._;
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// interface between D$ and processor
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class ioDmem(view: List[String] = null) extends Bundle(view) {
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val req_val = Bool('input);
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val req_rdy = Bool('output);
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val req_op = Bits(4, 'input);
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val req_addr = UFix(32, 'input);
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val req_data = Bits(64, 'input);
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val req_wmask = Bits(8, 'input);
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val req_tag = Bits(12, 'input);
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val resp_val = Bool('output);
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val resp_data = Bits(64, 'output);
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val resp_tag = Bits(12, 'output);
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}
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// interface between D$ and memory
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class ioDcache(view: List[String] = null) extends Bundle(view) {
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val req_addr = UFix(32, 'input);
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val req_tag = UFix(3, 'input);
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val req_val = Bool('input);
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val req_rdy = Bool('output);
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val req_wdata = Bits(128, 'input);
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val req_rw = Bool('input);
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val resp_data = Bits(128, 'output);
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val resp_tag = Bits(3, 'output);
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val resp_val = Bool('output);
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}
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class ioDCacheDM extends Bundle() {
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val cpu = new ioDmem();
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val mem = new ioDcache().flip();
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}
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// state machine to flush (write back dirty lines, invalidate clean ones) the D$
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class rocketDCacheDM_flush(lines: Int, addrbits: Int) extends Component {
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val io = new ioDCacheDM();
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val dcache = new rocketDCacheDM(lines, addrbits);
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val indexbits = ceil(log10(lines)/log10(2)).toInt;
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val offsetbits = 6;
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val tagmsb = addrbits - 1;
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val taglsb = indexbits+offsetbits;
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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val offsetlsb = 3;
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val flush_count = Reg(resetVal = UFix(0, indexbits));
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val flush_resp_count = Reg(resetVal = UFix(0, indexbits));
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val flushing = Reg(resetVal = Bool(false));
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val flush_waiting = Reg(resetVal = Bool(false));
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val r_cpu_req_tag = Reg(resetVal = Bits(0, 12));
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when (io.cpu.req_val && io.cpu.req_rdy && (io.cpu.req_op === M_FLA))
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{
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r_cpu_req_tag <== io.cpu.req_tag;
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flushing <== Bool(true);
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flush_waiting <== Bool(true);
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}
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when (dcache.io.cpu.req_rdy &&
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(flush_count === ~Bits(0, indexbits))) { flushing <== Bool(false); }
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when (dcache.io.cpu.resp_val &&
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(dcache.io.cpu.resp_tag === r_cpu_req_tag) &&
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(flush_resp_count === ~Bits(0, indexbits))) { flush_waiting <== Bool(false); }
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when (flushing && dcache.io.cpu.req_rdy) { flush_count <== flush_count + UFix(1,1); }
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when (flush_waiting && dcache.io.cpu.resp_val && (dcache.io.cpu.resp_tag === r_cpu_req_tag))
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{ flush_resp_count <== flush_resp_count + UFix(1,1); }
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dcache.io.cpu.req_val := (io.cpu.req_val && (io.cpu.req_op != M_FLA) && !flush_waiting) || flushing;
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dcache.io.cpu.req_op := Mux(flushing, M_FLA, io.cpu.req_op);
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dcache.io.cpu.req_addr := Mux(flushing, Cat(Bits(0,tagmsb-taglsb+1), flush_count, Bits(0,offsetbits)).toUFix, io.cpu.req_addr);
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dcache.io.cpu.req_tag := Mux(flushing, r_cpu_req_tag, io.cpu.req_tag);
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dcache.io.cpu.req_data ^^ io.cpu.req_data;
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dcache.io.cpu.req_wmask ^^ io.cpu.req_wmask;
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dcache.io.mem ^^ io.mem;
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io.cpu.req_rdy := dcache.io.cpu.req_rdy && !flush_waiting;
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io.cpu.resp_data := dcache.io.cpu.resp_data;
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io.cpu.resp_tag := dcache.io.cpu.resp_tag;
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io.cpu.resp_val := dcache.io.cpu.resp_val &
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!(flush_waiting && (io.cpu.resp_tag === r_cpu_req_tag) && (flush_count != ~Bits(0, addrbits)));
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}
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// basic direct mapped data cache, 2 cycle read latency
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// parameters :
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// lines = # of cache lines
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// addr_bits = address width (word addressable) bits
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// 64 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
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class rocketDCacheDM(lines: Int, addrbits: Int) extends Component {
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val io = new ioDCacheDM();
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val indexbits = ceil(log10(lines)/log10(2)).toInt;
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val offsetbits = 6;
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val tagmsb = addrbits - 1;
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val taglsb = indexbits+offsetbits;
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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val offsetlsb = 3;
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val s_reset :: s_ready :: s_start_writeback :: s_writeback :: s_req_refill :: s_refill :: s_resolve_miss :: Nil = Enum(7) { UFix() };
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val state = Reg(resetVal = s_reset);
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val r_cpu_req_addr = Reg(Bits(0, addrbits));
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val r_r_cpu_req_addr = Reg(r_cpu_req_addr);
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val r_cpu_req_val = Reg(Bool(false));
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val r_cpu_req_data = Reg(Bits(0,64));
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val r_cpu_req_op = Reg(Bits(0,4));
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val r_cpu_req_wmask = Reg(Bits(0,8));
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val r_cpu_req_tag = Reg(Bits(0,12));
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val r_cpu_resp_tag = Reg(r_cpu_req_tag);
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val r_cpu_resp_val = Reg(Bool(false));
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when (io.cpu.req_val && io.cpu.req_rdy) {
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r_cpu_req_addr <== io.cpu.req_addr;
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r_cpu_req_data <== io.cpu.req_data;
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r_cpu_req_op <== io.cpu.req_op;
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r_cpu_req_wmask <== io.cpu.req_wmask;
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r_cpu_req_tag <== io.cpu.req_tag; }
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val req_load = (r_cpu_req_op === M_XRD);
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val req_store = (r_cpu_req_op === M_XWR);
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val req_flush = (r_cpu_req_op === M_FLA);
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when (io.cpu.req_rdy) { r_cpu_req_val <== io.cpu.req_val; }
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otherwise { r_cpu_req_val <== Bool(false); }
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// counter
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val rr_count = Reg(resetVal = UFix(0,2));
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val rr_count_next = rr_count + UFix(1);
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when (((state === s_refill) && io.mem.resp_val) || ((state === s_writeback) && io.mem.req_rdy))
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{ rr_count <== rr_count_next; }
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// tag array
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val tag_we = (state === s_resolve_miss);
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val tag_waddr = r_cpu_req_addr(indexmsb, indexlsb).toUFix;
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val tag_wdata = r_cpu_req_addr(tagmsb, taglsb);
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val tag_array = Mem(lines, tag_we, tag_waddr, tag_wdata);
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val tag_raddr = Mux((state === s_ready), io.cpu.req_addr(indexmsb, indexlsb).toUFix, r_cpu_req_addr(indexmsb, indexlsb).toUFix);
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val tag_rdata = Reg(tag_array.read(tag_raddr));
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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val vb_rdata = Reg(vb_array(tag_raddr));
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when (tag_we && !req_flush) { vb_array <== vb_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(1,1)); }
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when (tag_we && req_flush) { vb_array <== vb_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(0,1)); }
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val tag_valid = vb_rdata.toBool;
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val tag_match = tag_valid && !req_flush && (tag_rdata === r_cpu_req_addr(tagmsb, taglsb));
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val store = ((state === s_ready) && r_cpu_req_val && req_store && tag_match ) ||
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((state === s_resolve_miss) && req_store);
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// dirty bit array
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val db_array = Reg(resetVal = Bits(0, lines));
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val db_rdata = Reg(db_array(tag_raddr));
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val tag_dirty = db_rdata.toBool;
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when (store) { db_array <== db_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(1,1)); }
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when (tag_we) { db_array <== db_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(0,1)); }
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// data array
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val data_array_we = ((state === s_refill) && io.mem.resp_val) || store;
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val data_array_waddr = Mux((state === s_refill),
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Cat(r_cpu_req_addr(indexmsb, indexlsb), rr_count).toUFix,
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r_cpu_req_addr(indexmsb, offsetmsb-1).toUFix);
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val data_array_wdata = Mux((state === s_refill), io.mem.resp_data, Cat(r_cpu_req_data, r_cpu_req_data));
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val req_wmask_expand = Cat(Fill(8, r_cpu_req_wmask(7)),
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Fill(8, r_cpu_req_wmask(6)),
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Fill(8, r_cpu_req_wmask(5)),
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Fill(8, r_cpu_req_wmask(4)),
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Fill(8, r_cpu_req_wmask(3)),
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Fill(8, r_cpu_req_wmask(2)),
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Fill(8, r_cpu_req_wmask(1)),
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Fill(8, r_cpu_req_wmask(0)));
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val store_wmask = Mux(r_cpu_req_addr(offsetlsb).toBool,
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Cat(req_wmask_expand, Bits(0,64)),
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Cat(Bits(0,64), req_wmask_expand));
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val data_array_wmask = Mux((state === s_refill), ~Bits(0,128), store_wmask);
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val data_array = Mem(lines*4, data_array_we, data_array_waddr, data_array_wdata, wrMask = data_array_wmask, resetVal = null);
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val data_array_raddr = Mux((state === s_writeback) && io.mem.req_rdy, Cat(r_cpu_req_addr(indexmsb, indexlsb), rr_count_next).toUFix,
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Mux((state === s_start_writeback) || (state === s_writeback), Cat(r_cpu_req_addr(indexmsb, indexlsb), rr_count).toUFix,
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r_cpu_req_addr(indexmsb, offsetmsb-1)));
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val data_array_rdata = Reg(data_array.read(data_array_raddr));
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// output signals
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io.cpu.req_rdy := (state === s_ready) && (!r_cpu_req_val || tag_match);
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when ((((state === s_ready) && r_cpu_req_val && tag_match) || (state === s_resolve_miss)) && !req_store)
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{ r_cpu_resp_val <== Bool(true); }
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otherwise { r_cpu_resp_val <== Bool(false); }
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io.cpu.resp_val := r_cpu_resp_val;
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io.cpu.resp_data := Mux(r_r_cpu_req_addr(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0));
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io.cpu.resp_tag := r_cpu_resp_tag;
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io.mem.req_val := (state === s_req_refill) || (state === s_writeback);
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io.mem.req_rw := (state === s_writeback);
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io.mem.req_wdata := data_array_rdata;
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io.mem.req_tag := UFix(0);
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io.mem.req_addr := Mux(state === s_writeback,
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Cat(tag_rdata, r_cpu_req_addr(indexmsb, indexlsb), rr_count).toUFix,
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Cat(r_cpu_req_addr(tagmsb, indexlsb), Bits(0,2)).toUFix);
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// control state machine
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switch (state) {
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is (s_reset) {
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state <== s_ready;
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}
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is (s_ready) {
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when (~r_cpu_req_val) { state <== s_ready; }
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when (r_cpu_req_val & tag_match) { state <== s_ready; }
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when (tag_valid & tag_dirty) { state <== s_start_writeback; }
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when (req_flush) { state <== s_resolve_miss; }
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otherwise { state <== s_req_refill; }
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}
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is (s_start_writeback) {
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state <== s_writeback;
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}
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is (s_writeback) {
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when (io.mem.req_rdy && (rr_count === UFix(3,2))) {
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when (req_flush) { state <== s_resolve_miss; }
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otherwise { state <== s_req_refill; }
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}
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}
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is (s_req_refill)
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{
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when (io.mem.req_rdy) { state <== s_refill; }
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}
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is (s_refill) {
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when (io.mem.resp_val && (rr_count === UFix(3,2))) { state <== s_resolve_miss; }
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}
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is (s_resolve_miss) {
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state <== s_ready;
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}
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}
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}
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}
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