2017-07-23 17:31:04 +02:00
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// See LICENSE.SiFive for license details.
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2018-01-12 21:29:27 +01:00
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package freechips.rocketchip.subsystem
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2017-07-23 17:31:04 +02:00
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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2018-02-15 23:01:49 +01:00
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case class SystemBusParams(beatBytes: Int, blockBytes: Int) extends HasTLBusParams
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2017-07-23 17:31:04 +02:00
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2017-09-09 03:33:44 +02:00
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case object SystemBusKey extends Field[SystemBusParams]
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2017-07-23 17:31:04 +02:00
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2018-02-21 02:09:30 +01:00
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class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "system_bus")
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2018-02-15 23:01:49 +01:00
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with HasTLXbarPhy {
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2017-08-08 02:30:24 +02:00
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2018-02-15 23:01:49 +01:00
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private val master_splitter = LazyModule(new TLSplitter)
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2017-07-29 09:01:26 +02:00
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inwardNode :=* master_splitter.node
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2017-07-23 17:31:04 +02:00
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2018-02-15 23:01:49 +01:00
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def busView = master_splitter.node.edges.in.head
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2017-09-06 01:41:39 +02:00
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2018-02-15 23:01:49 +01:00
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private def bufferTo(buffer: BufferParams): TLOutwardNode =
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TLBuffer(buffer) :*= delayNode :*= outwardNode
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2017-07-23 17:31:04 +02:00
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2018-02-21 23:40:26 +01:00
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private def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
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TLWidthWidget(params.beatBytes) :*= bufferTo(buffer)
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2018-02-15 23:01:49 +01:00
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def toPeripheryBus(buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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2018-02-21 02:09:30 +01:00
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to("pbus") {
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2018-02-15 23:01:49 +01:00
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(gen
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:= TLFIFOFixer(TLFIFOFixer.all)
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:= TLWidthWidget(params.beatBytes)
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:= bufferTo(buffer))
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}
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}
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2017-07-23 17:31:04 +02:00
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2018-02-15 23:01:49 +01:00
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def toMemoryBus(gen: => TLInwardNode) {
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2018-02-21 02:09:30 +01:00
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to("mbus") { gen :*= delayNode :*= outwardNode }
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2017-08-31 02:57:52 +02:00
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}
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2017-07-23 17:31:04 +02:00
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2018-02-15 23:01:49 +01:00
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def toSlave(name: Option[String] = None, buffer: BufferParams = BufferParams.default)
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(gen: => TLNode): TLOutwardNode = {
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2018-02-21 02:09:30 +01:00
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to("slave" named name) { gen :*= bufferTo(buffer) }
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2018-02-15 23:01:49 +01:00
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}
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def toSplitSlave(name: Option[String] = None)
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(gen: => TLNode): TLOutwardNode = {
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2018-02-22 03:22:06 +01:00
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to("slave" named name) { gen :=* master_splitter.node }
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2018-02-15 23:01:49 +01:00
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}
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2017-07-23 17:31:04 +02:00
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2018-02-21 23:40:26 +01:00
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def toFixedWidthSlave(
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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to("slave" named name) { gen :*= fixedWidthTo(buffer) }
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}
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2018-02-15 23:01:49 +01:00
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def toVariableWidthSlave(
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.default)
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(gen: => TLNode): TLOutwardNode = {
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2018-02-21 02:09:30 +01:00
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to("slave" named name) {
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2018-02-15 23:01:49 +01:00
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gen :*= TLFragmenter(params.beatBytes, params.blockBytes) :*= bufferTo(buffer)
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}
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}
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2017-07-27 20:10:34 +02:00
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2018-02-15 23:01:49 +01:00
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def fromFrontBus(gen: => TLNode): TLInwardNode = {
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2018-02-22 03:22:06 +01:00
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from("front_bus") { master_splitter.node :=* gen }
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2018-02-15 23:01:49 +01:00
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}
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2017-09-06 00:02:16 +02:00
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2018-02-15 23:01:49 +01:00
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def fromTile(
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name: Option[String],
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buffers: Int = 0,
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cork: Option[Boolean] = None)
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(gen: => TLNode): TLInwardNode = {
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2018-02-21 02:09:30 +01:00
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from("tile" named name) {
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2018-02-17 00:58:55 +01:00
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(List(master_splitter.node, TLFIFOFixer(TLFIFOFixer.allUncacheable)) ++ TLBuffer.chain(buffers))
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.reduce(_ :=* _) :=* gen
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2017-10-23 18:39:01 +02:00
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}
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2017-07-23 17:31:04 +02:00
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}
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2018-02-15 23:01:49 +01:00
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def toFixedWidthPort[D,U,E,B <: Data](
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.default)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
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2018-02-21 23:40:26 +01:00
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to("port" named name) { gen := fixedWidthTo(buffer) }
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2017-07-23 17:31:04 +02:00
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}
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2018-02-15 23:01:49 +01:00
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def fromPort[D,U,E,B <: Data](
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name: Option[String] = None,
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buffers: Int = 0)
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(gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle]): InwardNodeHandle[D,U,E,B] = {
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2018-02-21 02:09:30 +01:00
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from("port" named name) {
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2018-02-15 23:01:49 +01:00
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(List(
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master_splitter.node,
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TLFIFOFixer(TLFIFOFixer.all)) ++
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TLBuffer.chain(buffers)).reduce(_ :=* _) :=* gen
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}
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2017-08-24 23:42:30 +02:00
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}
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2018-02-21 23:40:26 +01:00
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2018-02-22 03:22:06 +01:00
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def fromCoherentMaster(
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name: Option[String] = None,
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buffers: Int = 0)
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(gen: => TLNode): TLInwardNode = {
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from("coherent_master" named name) {
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(inwardNode
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:=* TLFIFOFixer(TLFIFOFixer.all)
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:=* TLBuffer.chain(buffers).reduce(_ :=* _)
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:=* gen)
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}
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}
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2018-02-21 23:40:26 +01:00
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def fromMaster(
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name: Option[String] = None,
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buffers: Int = 0)
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(gen: => TLNode): TLInwardNode = {
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from("master" named name) {
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2018-02-22 03:22:06 +01:00
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(master_splitter.node
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:=* TLFIFOFixer(TLFIFOFixer.all)
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:=* TLBuffer.chain(buffers).reduce(_ :=* _)
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:=* gen)
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2018-02-21 23:40:26 +01:00
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}
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}
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2017-07-23 17:31:04 +02:00
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}
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