2016-11-28 01:16:37 +01:00
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// See LICENSE.SiFive for license details.
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2016-09-15 03:10:21 +02:00
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2016-09-15 22:04:01 +02:00
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package unittest
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2016-09-15 03:10:21 +02:00
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import Chisel._
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2016-11-18 23:05:14 +01:00
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import config._
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2016-09-22 23:31:45 +02:00
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import rocketchip.{BaseConfig, BasePlatformConfig}
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2016-09-15 03:10:21 +02:00
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2017-01-13 23:41:19 +01:00
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class WithUncoreUnitTests extends Config((site, here, up) => {
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case uncore.tilelink.TLId => "L1toL2"
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.tilelink2.TLFuzzRAMTest),
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Module(new uncore.ahb.AHBBridgeTest),
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Module(new uncore.apb.APBBridgeTest),
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Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
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Module(new uncore.axi4.AXI4FullFuzzRAMTest),
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Module(new uncore.axi4.AXI4BridgeTest)) }
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})
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2016-09-15 03:10:21 +02:00
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2017-01-17 03:24:08 +01:00
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class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new BasePlatformConfig)
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2016-09-29 00:11:05 +02:00
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2017-01-13 23:41:19 +01:00
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class WithTLSimpleUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.tilelink2.TLRAMSimpleTest(1)),
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Module(new uncore.tilelink2.TLRAMSimpleTest(4)),
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Module(new uncore.tilelink2.TLRAMSimpleTest(16)),
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Module(new uncore.tilelink2.TLRR0Test),
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Module(new uncore.tilelink2.TLRR1Test),
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2017-01-26 23:32:27 +01:00
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Module(new uncore.tilelink2.TLRAMAsyncCrossingTest) ) }
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2017-01-13 23:41:19 +01:00
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})
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2016-09-29 02:15:12 +02:00
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2017-01-13 23:41:19 +01:00
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class WithTLWidthUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256)),
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Module(new uncore.tilelink2.TLRAMFragmenterTest(16, 64)),
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Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 16)),
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Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1, 1)),
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Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64)),
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Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64, 4)) ) }
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})
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2016-09-29 02:15:12 +02:00
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2017-01-13 23:41:19 +01:00
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class WithTLXbarUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.tilelink2.TLRAMXbarTest(1)),
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Module(new uncore.tilelink2.TLRAMXbarTest(2)),
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Module(new uncore.tilelink2.TLRAMXbarTest(8)),
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//Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4)),
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Module(new uncore.tilelink2.TLMulticlientXbarTest(1,4)) ) }
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})
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2016-09-29 00:11:05 +02:00
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2016-09-29 02:15:12 +02:00
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class TLSimpleUnitTestConfig extends Config(new WithTLSimpleUnitTests ++ new BasePlatformConfig)
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class TLWidthUnitTestConfig extends Config(new WithTLWidthUnitTests ++ new BasePlatformConfig)
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class TLXbarUnitTestConfig extends Config(new WithTLXbarUnitTests ++ new BasePlatformConfig)
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