2016-09-15 03:10:21 +02:00
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// See LICENSE for license details.
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2016-09-15 22:04:01 +02:00
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package unittest
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2016-09-15 03:10:21 +02:00
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import Chisel._
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2016-09-15 23:25:47 +02:00
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import cde.{Parameters, Config, CDEMatchError}
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2016-09-22 02:40:39 +02:00
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import coreplex.{TestGeneration, DefaultTestSuites}
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import rocketchip.BaseConfig
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2016-09-15 03:10:21 +02:00
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2016-09-20 23:14:30 +02:00
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class WithJunctionsUnitTests extends Config(
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2016-09-15 03:10:21 +02:00
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(pname, site, here) => pname match {
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2016-09-20 23:14:30 +02:00
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case UnitTests => (p: Parameters) => {
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2016-09-15 23:25:47 +02:00
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TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why
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2016-09-15 03:10:21 +02:00
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TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
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2016-09-20 23:14:30 +02:00
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Seq(
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Module(new junctions.MultiWidthFifoTest),
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Module(new junctions.NastiMemoryDemuxTest()(p)),
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Module(new junctions.HastiTest()(p)))
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2016-09-15 03:10:21 +02:00
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}
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2016-09-20 23:14:30 +02:00
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case _ => throw new CDEMatchError
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})
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class WithUncoreUnitTests extends Config(
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(pname, site, here) => pname match {
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2016-09-22 02:40:39 +02:00
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case rocketchip.NCoreplexExtClients => 0
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2016-09-20 23:14:30 +02:00
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case uncore.tilelink.TLId => "L1toL2"
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case UnitTests => (p: Parameters) => {
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TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why
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TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
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Seq(
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Module(new uncore.devices.ROMSlaveTest()(p)),
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Module(new uncore.devices.TileLinkRAMTest()(p)),
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2016-09-22 02:11:57 +02:00
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Module(new uncore.tilelink2.TLFuzzRAMTest)
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)
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2016-09-20 23:14:30 +02:00
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}
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2016-09-15 03:10:21 +02:00
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case _ => throw new CDEMatchError
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2016-09-22 02:11:57 +02:00
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}
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)
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2016-09-15 03:10:21 +02:00
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2016-09-20 23:14:30 +02:00
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class UnitTestConfig extends Config(new WithUncoreUnitTests ++ new WithJunctionsUnitTests ++ new BaseConfig)
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