2015-07-08 05:38:47 +02:00
|
|
|
// See LICENSE for license details.
|
|
|
|
|
|
|
|
package rocketchip
|
|
|
|
|
|
|
|
import Chisel._
|
2015-07-30 02:56:19 +02:00
|
|
|
import junctions._
|
2015-07-08 05:38:47 +02:00
|
|
|
import uncore._
|
|
|
|
import rocket._
|
|
|
|
import zscale._
|
|
|
|
|
2015-07-14 00:46:42 +02:00
|
|
|
case object UseZscale extends Field[Boolean]
|
|
|
|
case object BuildZscale extends Field[(Bool) => Zscale]
|
2015-07-17 21:02:02 +02:00
|
|
|
case object BootROMCapacity extends Field[Int]
|
|
|
|
case object DRAMCapacity extends Field[Int]
|
2015-07-14 00:46:42 +02:00
|
|
|
|
2015-07-08 05:38:47 +02:00
|
|
|
class ZscaleSystem extends Module {
|
|
|
|
val io = new Bundle {
|
|
|
|
val host = new HTIFIO
|
|
|
|
val jtag = new HASTIMasterIO().flip
|
|
|
|
val bootmem = new HASTISlaveIO().flip
|
|
|
|
val dram = new HASTISlaveIO().flip
|
|
|
|
val spi = new HASTISlaveIO().flip
|
|
|
|
val led = new POCIIO
|
|
|
|
val corereset = new POCIIO
|
|
|
|
}
|
|
|
|
|
2015-07-14 00:46:42 +02:00
|
|
|
val core = params(BuildZscale)(io.host.reset)
|
2015-07-08 05:38:47 +02:00
|
|
|
|
|
|
|
val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0)
|
|
|
|
|
|
|
|
val sbus_afn = (addr: UInt) => addr(31, 29).orR
|
|
|
|
val dram_afn = (addr: UInt) => addr(31, 26) === UInt(8)
|
|
|
|
val spi_afn = (addr: UInt) => addr(31, 26) === UInt(9) && addr(25, 14) === UInt(0)
|
|
|
|
|
|
|
|
val pbus_afn = (addr: UInt) => addr(31) === UInt(1)
|
|
|
|
val led_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(0)
|
|
|
|
val corereset_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(1)
|
|
|
|
|
|
|
|
val xbar = Module(new HASTIXbar(3, Seq(bootmem_afn, sbus_afn)))
|
|
|
|
val sadapter = Module(new HASTISlaveToMaster)
|
|
|
|
val sbus = Module(new HASTIBus(Seq(dram_afn, spi_afn, pbus_afn)))
|
|
|
|
val padapter = Module(new HASTItoPOCIBridge)
|
|
|
|
val pbus = Module(new POCIBus(Seq(led_afn, corereset_afn)))
|
|
|
|
|
|
|
|
core.io.host <> io.host
|
|
|
|
xbar.io.masters(0) <> io.jtag
|
|
|
|
xbar.io.masters(1) <> core.io.dmem
|
|
|
|
xbar.io.masters(2) <> core.io.imem
|
|
|
|
|
|
|
|
io.bootmem <> xbar.io.slaves(0)
|
|
|
|
sadapter.io.in <> xbar.io.slaves(1)
|
|
|
|
|
|
|
|
sbus.io.master <> sadapter.io.out
|
|
|
|
io.dram <> sbus.io.slaves(0)
|
|
|
|
io.spi <> sbus.io.slaves(1)
|
|
|
|
padapter.io.in <> sbus.io.slaves(2)
|
|
|
|
|
|
|
|
pbus.io.master <> padapter.io.out
|
|
|
|
io.led <> pbus.io.slaves(0)
|
|
|
|
io.corereset <> pbus.io.slaves(1)
|
|
|
|
}
|
|
|
|
|
|
|
|
class ZscaleTop extends Module {
|
|
|
|
val io = new Bundle {
|
|
|
|
val host = new HTIFIO
|
|
|
|
}
|
|
|
|
|
|
|
|
val sys = Module(new ZscaleSystem)
|
2015-07-17 21:02:02 +02:00
|
|
|
val bootmem = Module(new HASTISRAM(params(BootROMCapacity)/4))
|
|
|
|
val dram = Module(new HASTISRAM(params(DRAMCapacity)/4))
|
2015-07-08 05:38:47 +02:00
|
|
|
|
|
|
|
sys.io.host <> io.host
|
|
|
|
bootmem.io <> sys.io.bootmem
|
|
|
|
dram.io <> sys.io.dram
|
|
|
|
}
|