1
0
rocket-chip/rocket/src/main/scala/tlb.scala

186 lines
6.3 KiB
Scala
Raw Normal View History

2014-09-13 03:06:41 +02:00
// See LICENSE for license details.
2012-10-10 06:35:03 +02:00
package rocket
import Chisel._
2015-03-14 10:49:07 +01:00
import Util._
import junctions._
import scala.math._
2015-10-22 03:18:32 +02:00
import cde.{Parameters, Field}
import uncore.agents.PseudoLRU
import uncore.coherence._
2012-10-10 06:35:03 +02:00
case object NTLBEntries extends Field[Int]
2016-03-11 02:32:00 +01:00
trait HasTLBParameters extends HasCoreParameters {
2015-10-06 06:48:05 +02:00
val entries = p(NTLBEntries)
2015-10-07 03:22:23 +02:00
val camAddrBits = log2Ceil(entries)
val camTagBits = asIdBits + vpnBits
}
2015-10-06 06:48:05 +02:00
class TLBReq(implicit p: Parameters) extends CoreBundle()(p) {
2016-03-11 02:32:00 +01:00
val vpn = UInt(width = vpnBitsExtended)
val passthrough = Bool()
2012-10-10 06:35:03 +02:00
val instruction = Bool()
2015-03-14 10:49:07 +01:00
val store = Bool()
2012-10-10 06:35:03 +02:00
}
2016-07-02 23:26:05 +02:00
class TLBResp(implicit p: Parameters) extends CoreBundle()(p) {
2012-10-10 06:35:03 +02:00
// lookup responses
val miss = Bool(OUTPUT)
val ppn = UInt(OUTPUT, ppnBits)
2012-10-10 06:35:03 +02:00
val xcpt_ld = Bool(OUTPUT)
val xcpt_st = Bool(OUTPUT)
val xcpt_if = Bool(OUTPUT)
val cacheable = Bool(OUTPUT)
2012-10-10 06:35:03 +02:00
}
2016-07-02 23:26:05 +02:00
class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
2012-10-10 06:35:03 +02:00
val io = new Bundle {
2013-08-12 19:39:11 +02:00
val req = Decoupled(new TLBReq).flip
val resp = new TLBResp
2013-01-07 22:38:59 +01:00
val ptw = new TLBPTWIO
2012-10-10 06:35:03 +02:00
}
2016-07-02 23:26:05 +02:00
val valid = Reg(init = UInt(0, entries))
val ppns = Reg(Vec(entries, UInt(width = ppnBits)))
2016-07-02 23:26:05 +02:00
val tags = Reg(Vec(entries, UInt(width = asIdBits + vpnBits)))
2016-03-31 07:48:31 +02:00
2013-09-10 19:51:35 +02:00
val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(UInt(), 4)
2013-08-16 00:28:15 +02:00
val state = Reg(init=s_ready)
2016-07-02 23:26:05 +02:00
val r_refill_tag = Reg(UInt(width = asIdBits + vpnBits))
val r_refill_waddr = Reg(UInt(width = log2Ceil(entries)))
2015-03-14 10:49:07 +01:00
val r_req = Reg(new TLBReq)
val do_mprv = io.ptw.status.mprv && !io.req.bits.instruction
val priv = Mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv)
val priv_s = priv === PRV.S
val priv_uses_vm = priv <= PRV.S && !io.ptw.status.debug
// share a single physical memory attribute checker (unshare if critical path)
val passthrough_ppn = io.req.bits.vpn(ppnBits-1, 0)
val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0)
val do_refill = Bool(usingVM) && io.ptw.resp.valid
val mpu_ppn = Mux(do_refill, refill_ppn, passthrough_ppn)
val prot = addrMap.getProt(mpu_ppn << pgIdxBits)
val cacheable = addrMap.isCacheable(mpu_ppn << pgIdxBits)
require(addrMap.flatten.forall { case (n, r) => (r.start | r.size) % (1 << pgIdxBits) == 0 })
2012-10-10 06:35:03 +02:00
val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0))
val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
val hitsVec = (0 until entries).map(i => valid(i) && vm_enabled && tags(i) === lookup_tag) :+ !vm_enabled
val hits = hitsVec.asUInt
2012-10-10 06:35:03 +02:00
// permission bit arrays
2016-07-06 04:19:49 +02:00
val pte_array = Reg(new PTE)
val u_array = Reg(UInt(width = entries)) // user permission
val sw_array = Reg(UInt(width = entries)) // write permission
val sx_array = Reg(UInt(width = entries)) // execute permission
val sr_array = Reg(UInt(width = entries)) // read permission
val xr_array = Reg(UInt(width = entries)) // read permission to executable page
val cash_array = Reg(UInt(width = entries)) // cacheable
2016-07-02 23:26:05 +02:00
val dirty_array = Reg(UInt(width = entries)) // PTE dirty bit
when (do_refill) {
val pte = io.ptw.resp.bits.pte
2016-07-02 23:26:05 +02:00
ppns(r_refill_waddr) := pte.ppn
tags(r_refill_waddr) := r_refill_tag
val mask = UIntToOH(r_refill_waddr)
valid := valid | mask
2016-07-06 04:19:49 +02:00
u_array := Mux(pte.u, u_array | mask, u_array & ~mask)
sw_array := Mux(pte.sw() && prot.w, sw_array | mask, sw_array & ~mask)
sx_array := Mux(pte.sx() && prot.x, sx_array | mask, sx_array & ~mask)
sr_array := Mux(pte.sr() && prot.r, sr_array | mask, sr_array & ~mask)
xr_array := Mux(pte.sx() && prot.r, xr_array | mask, xr_array & ~mask)
cash_array := Mux(cacheable, cash_array | mask, cash_array & ~mask)
2016-07-02 23:26:05 +02:00
dirty_array := Mux(pte.d, dirty_array | mask, dirty_array & ~mask)
2012-10-10 06:35:03 +02:00
}
val plru = new PseudoLRU(entries)
2016-07-02 23:26:05 +02:00
val repl_waddr = Mux(!valid.andR, PriorityEncoder(~valid), plru.replace)
2016-03-03 08:29:58 +01:00
2016-07-06 04:19:49 +02:00
val priv_ok = Mux(priv_s, ~Mux(io.ptw.status.pum, u_array, UInt(0)), u_array)
val w_array = Cat(prot.w, priv_ok & sw_array)
val x_array = Cat(prot.x, priv_ok & sx_array)
val r_array = Cat(prot.r, priv_ok & (sr_array | Mux(io.ptw.status.mxr, xr_array, UInt(0))))
val c_array = Cat(cacheable, cash_array)
2015-03-14 10:49:07 +01:00
2016-03-11 02:32:00 +01:00
val bad_va =
if (vpnBits == vpnBitsExtended) Bool(false)
else io.req.bits.vpn(vpnBits) =/= io.req.bits.vpn(vpnBits-1)
2015-03-14 10:49:07 +01:00
// it's only a store hit if the dirty bit is set
val tlb_hits = hits(entries-1, 0) & (dirty_array | ~Mux(io.req.bits.store, w_array, UInt(0)))
val tlb_hit = tlb_hits.orR
val tlb_miss = vm_enabled && !bad_va && !tlb_hit
when (io.req.valid && !tlb_miss) {
plru.access(OHToUInt(hits(entries-1, 0)))
2012-10-10 06:35:03 +02:00
}
io.req.ready := state === s_ready
io.resp.xcpt_ld := bad_va || (~r_array & hits).orR
io.resp.xcpt_st := bad_va || (~w_array & hits).orR
io.resp.xcpt_if := bad_va || (~x_array & hits).orR
io.resp.cacheable := (c_array & hits).orR
io.resp.miss := do_refill || tlb_miss
io.resp.ppn := Mux1H(hitsVec, ppns :+ passthrough_ppn)
2015-03-14 10:49:07 +01:00
2012-10-10 06:35:03 +02:00
io.ptw.req.valid := state === s_request
2016-07-06 04:19:49 +02:00
io.ptw.req.bits := io.ptw.status
2015-03-14 10:49:07 +01:00
io.ptw.req.bits.addr := r_refill_tag
io.ptw.req.bits.store := r_req.store
io.ptw.req.bits.fetch := r_req.instruction
2012-10-10 06:35:03 +02:00
2016-03-25 22:17:25 +01:00
if (usingVM) {
when (io.req.fire() && tlb_miss) {
state := s_request
r_refill_tag := lookup_tag
r_refill_waddr := repl_waddr
r_req := io.req.bits
2012-10-10 06:35:03 +02:00
}
2016-03-25 22:17:25 +01:00
when (state === s_request) {
when (io.ptw.invalidate) {
state := s_ready
}
when (io.ptw.req.ready) {
state := s_wait
when (io.ptw.invalidate) { state := s_wait_invalidate }
}
}
when (state === s_wait && io.ptw.invalidate) {
state := s_wait_invalidate
}
when (io.ptw.resp.valid) {
state := s_ready
2012-10-10 06:35:03 +02:00
}
2016-07-02 23:26:05 +02:00
when (io.ptw.invalidate) {
valid := 0
}
2012-10-10 06:35:03 +02:00
}
}
class DecoupledTLB(implicit p: Parameters) extends Module {
val io = new Bundle {
val req = Decoupled(new TLBReq).flip
val resp = Decoupled(new TLBResp)
val ptw = new TLBPTWIO
}
val reqq = Queue(io.req)
val tlb = Module(new TLB)
val resp_helper = DecoupledHelper(
reqq.valid, tlb.io.req.ready, io.resp.ready)
val tlb_miss = tlb.io.resp.miss
tlb.io.req.valid := resp_helper.fire(tlb.io.req.ready)
tlb.io.req.bits := reqq.bits
reqq.ready := resp_helper.fire(reqq.valid, !tlb_miss)
io.resp.valid := resp_helper.fire(io.resp.ready, !tlb_miss)
io.resp.bits := tlb.io.resp
io.ptw <> tlb.io.ptw
}