2016-11-28 01:16:37 +01:00
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// See LICENSE.SiFive for license details.
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2016-11-16 03:27:52 +01:00
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package rocketchip
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import Chisel._
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2016-11-18 23:05:14 +01:00
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import config._
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2016-11-16 03:27:52 +01:00
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import diplomacy._
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import uncore.tilelink2._
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import uncore.devices._
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import util._
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2017-03-28 06:19:08 +02:00
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import jtag.JTAGIO
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2016-11-16 03:27:52 +01:00
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import coreplex._
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2017-03-28 06:19:08 +02:00
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// System with JTAG DTM Instantiated inside. JTAG interface is
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// exported outside.
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2016-11-24 00:35:53 +01:00
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2017-03-28 06:19:08 +02:00
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trait PeripheryJTAGDTM extends HasTopLevelNetworks {
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val module: PeripheryJTAGDTMModule
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2016-11-16 03:27:52 +01:00
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val coreplex: CoreplexRISCVPlatform
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}
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2017-03-28 06:19:08 +02:00
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trait PeripheryJTAGDTMBundle extends HasTopLevelNetworksBundle {
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val outer: PeripheryJTAGDTM
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val jtag = new JTAGIO(hasTRSTn = false).flip
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val jtag_reset = Bool(INPUT)
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2017-04-14 01:12:22 +02:00
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val jtag_mfr_id = UInt(INPUT, 11)
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2016-11-16 03:27:52 +01:00
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}
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2017-03-28 06:19:08 +02:00
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trait PeripheryJTAGDTMModule extends HasTopLevelNetworksModule {
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val outer: PeripheryJTAGDTM
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val io: PeripheryJTAGDTMBundle
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2016-11-16 03:27:52 +01:00
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2017-03-28 06:19:08 +02:00
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val dtm = Module (new DebugTransportModuleJTAG(p(DMKey).nDMIAddrSize, p(JtagDTMKey)))
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2016-11-16 03:27:52 +01:00
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dtm.io.jtag <> io.jtag
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2017-03-28 06:19:08 +02:00
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dtm.clock := io.jtag.TCK
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dtm.io.jtag_reset := io.jtag_reset
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2017-04-14 01:12:22 +02:00
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dtm.io.jtag_mfr_id := io.jtag_mfr_id
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2017-03-28 06:19:08 +02:00
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dtm.reset := dtm.io.fsmReset
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outer.coreplex.module.io.debug.dmi <> dtm.io.dmi
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outer.coreplex.module.io.debug.dmiClock := io.jtag.TCK
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outer.coreplex.module.io.debug.dmiReset := ResetCatchAndSync(io.jtag.TCK, io.jtag_reset, "dmiResetCatch")
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2016-11-16 03:27:52 +01:00
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}
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2017-03-28 06:19:08 +02:00
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// System with Debug Module Interface Only. Any sort of DTM
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// can be connected outside. DMI Clock and Reset must be provided.
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2016-11-24 00:35:53 +01:00
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2017-03-28 06:19:08 +02:00
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trait PeripheryDMI extends HasTopLevelNetworks {
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val module: PeripheryDMIModule
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2016-11-16 03:27:52 +01:00
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val coreplex: CoreplexRISCVPlatform
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}
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2017-03-28 06:19:08 +02:00
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trait PeripheryDMIBundle extends HasTopLevelNetworksBundle {
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val outer: PeripheryDMI
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2016-11-16 03:27:52 +01:00
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2017-03-28 06:19:08 +02:00
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val debug = new ClockedDMIIO().flip
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2016-11-16 03:27:52 +01:00
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}
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2017-03-28 06:19:08 +02:00
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trait PeripheryDMIModule extends HasTopLevelNetworksModule {
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val outer: PeripheryDMI
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val io: PeripheryDMIBundle
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2016-11-16 03:27:52 +01:00
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2017-03-28 06:19:08 +02:00
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outer.coreplex.module.io.debug <> io.debug
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2016-11-16 03:27:52 +01:00
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}
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2017-03-28 06:19:08 +02:00
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// System with DMI or JTAG interface based on a parameter
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2016-11-24 00:35:53 +01:00
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2017-02-23 23:25:17 +01:00
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trait PeripheryDebug extends HasTopLevelNetworks {
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2016-11-24 00:35:53 +01:00
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val module: PeripheryDebugModule
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val coreplex: CoreplexRISCVPlatform
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}
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2017-02-23 23:25:17 +01:00
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trait PeripheryDebugBundle extends HasTopLevelNetworksBundle {
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2016-11-24 00:35:53 +01:00
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val outer: PeripheryDebug
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2017-03-28 06:19:08 +02:00
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val debug = (!p(IncludeJtagDTM)).option(new ClockedDMIIO().flip)
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val jtag = (p(IncludeJtagDTM)).option(new JTAGIO(hasTRSTn = false).flip)
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val jtag_reset = (p(IncludeJtagDTM)).option(Bool(INPUT))
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2017-04-14 01:12:22 +02:00
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val jtag_mfr_id = (p(IncludeJtagDTM)).option(UInt(INPUT, 11))
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2017-03-28 06:19:08 +02:00
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2017-04-03 22:31:35 +02:00
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val ndreset = Bool(OUTPUT)
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val dmactive = Bool(OUTPUT)
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2016-11-24 00:35:53 +01:00
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}
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2017-02-23 23:25:17 +01:00
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trait PeripheryDebugModule extends HasTopLevelNetworksModule {
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2016-11-24 00:35:53 +01:00
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val outer: PeripheryDebug
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val io: PeripheryDebugBundle
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2017-03-28 06:19:08 +02:00
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io.debug.foreach { dbg => outer.coreplex.module.io.debug <> dbg }
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val dtm = if (io.jtag.isDefined) Some[DebugTransportModuleJTAG](Module (new DebugTransportModuleJTAG(p(DMKey).nDMIAddrSize, p(JtagDTMKey)))) else None
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dtm.foreach { dtm =>
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dtm.io.jtag <> io.jtag.get
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dtm.clock := io.jtag.get.TCK
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dtm.io.jtag_reset := io.jtag_reset.get
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2017-04-14 01:12:22 +02:00
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dtm.io.jtag_mfr_id := io.jtag_mfr_id.get
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2017-03-28 06:19:08 +02:00
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dtm.reset := dtm.io.fsmReset
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outer.coreplex.module.io.debug.dmi <> dtm.io.dmi
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outer.coreplex.module.io.debug.dmiClock := io.jtag.get.TCK
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outer.coreplex.module.io.debug.dmiReset := ResetCatchAndSync(io.jtag.get.TCK, io.jtag_reset.get, "dmiResetCatch")
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2016-11-24 00:35:53 +01:00
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}
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2017-04-03 22:31:35 +02:00
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io.ndreset := outer.coreplex.module.io.ndreset
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io.dmactive := outer.coreplex.module.io.dmactive
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2016-11-24 00:35:53 +01:00
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}
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/// Real-time clock is based on RTCPeriod relative to Top clock
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2017-02-23 23:25:17 +01:00
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trait PeripheryCounter extends HasTopLevelNetworks {
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2016-11-16 03:27:52 +01:00
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val module: PeripheryCounterModule
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val coreplex: CoreplexRISCVPlatform
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}
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2017-02-23 23:25:17 +01:00
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trait PeripheryCounterBundle extends HasTopLevelNetworksBundle {
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2016-11-16 03:27:52 +01:00
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val outer: PeripheryCounter
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}
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2017-02-23 23:25:17 +01:00
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trait PeripheryCounterModule extends HasTopLevelNetworksModule {
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2016-11-16 03:27:52 +01:00
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val outer: PeripheryCounter
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val io: PeripheryCounterBundle
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{
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val period = p(rocketchip.RTCPeriod)
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val rtcCounter = RegInit(UInt(0, width = log2Up(period)))
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val rtcWrap = rtcCounter === UInt(period-1)
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rtcCounter := Mux(rtcWrap, UInt(0), rtcCounter + UInt(1))
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outer.coreplex.module.io.rtcToggle := rtcCounter(log2Up(period)-1)
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}
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}
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2016-11-24 00:35:53 +01:00
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/// Coreplex will power-on running at 0x1000 (BootROM)
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2017-02-23 23:25:17 +01:00
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trait HardwiredResetVector extends HasTopLevelNetworks {
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2016-11-16 03:27:52 +01:00
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val module: HardwiredResetVectorModule
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val coreplex: CoreplexRISCVPlatform
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}
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2017-02-23 23:25:17 +01:00
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trait HardwiredResetVectorBundle extends HasTopLevelNetworksBundle {
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2016-11-16 03:27:52 +01:00
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val outer: HardwiredResetVector
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}
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2017-02-23 23:25:17 +01:00
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trait HardwiredResetVectorModule extends HasTopLevelNetworksModule {
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2016-11-16 03:27:52 +01:00
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val outer: HardwiredResetVector
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val io: HardwiredResetVectorBundle
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2017-03-25 00:00:00 +01:00
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outer.coreplex.module.io.resetVector := UInt(0x10040) // boot ROM: hang
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2016-11-16 03:27:52 +01:00
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}
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