2014-09-01 05:26:55 +02:00
|
|
|
#=======================================================================
|
|
|
|
|
# Makefile for Verilog simulation w/ VCS
|
|
|
|
|
#-----------------------------------------------------------------------
|
|
|
|
|
# Yunsup Lee (yunsup@cs.berkeley.edu)
|
|
|
|
|
#
|
|
|
|
|
# This makefile will build a rtl simulator and run various tests to
|
|
|
|
|
# verify proper functionality.
|
|
|
|
|
#
|
|
|
|
|
|
|
|
|
|
default: all
|
|
|
|
|
|
|
|
|
|
base_dir = $(abspath ..)
|
|
|
|
|
generated_dir = $(abspath ./generated-src)
|
2014-09-08 09:21:57 +02:00
|
|
|
mem_gen = $(base_dir)/vsim/vlsi_mem_gen
|
2014-09-01 05:26:55 +02:00
|
|
|
sim_dir = .
|
|
|
|
|
output_dir = $(sim_dir)/output
|
|
|
|
|
|
2014-09-17 19:48:56 +02:00
|
|
|
BACKEND ?= rocketchip.RocketChipBackend
|
|
|
|
|
CONFIG ?= DefaultVLSIConfig
|
2015-07-17 21:02:02 +02:00
|
|
|
TB ?= rocketTestHarness
|
2014-09-08 09:21:57 +02:00
|
|
|
|
2014-09-04 02:28:45 +02:00
|
|
|
include $(base_dir)/Makefrag
|
2014-09-04 18:49:57 +02:00
|
|
|
include $(sim_dir)/Makefrag
|
2015-07-28 09:23:31 +02:00
|
|
|
-include $(generated_dir)/$(MODEL).$(CONFIG).d
|
|
|
|
|
include $(base_dir)/vsim/Makefrag-verilog
|
2014-09-01 05:26:55 +02:00
|
|
|
|
|
|
|
|
all: $(simv)
|
2014-09-12 07:11:58 +02:00
|
|
|
debug: $(simv_debug)
|
2014-09-01 05:26:55 +02:00
|
|
|
|
|
|
|
|
clean:
|
2014-09-04 18:49:57 +02:00
|
|
|
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)
|
2014-09-12 07:11:58 +02:00
|
|
|
|
|
|
|
|
.PHONY: default all debug clean
|
