2016-11-28 01:16:37 +01:00
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// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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2014-09-13 03:06:41 +02:00
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2017-07-23 17:31:04 +02:00
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package freechips.rocketchip.tile
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2012-03-25 00:56:59 +01:00
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import Chisel._
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2017-07-07 19:48:16 +02:00
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import freechips.rocketchip.config._
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2017-12-28 23:00:13 +01:00
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import freechips.rocketchip.coreplex.CoreplexClockCrossing
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2017-07-07 19:48:16 +02:00
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import freechips.rocketchip.diplomacy._
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2017-07-23 17:31:04 +02:00
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import freechips.rocketchip.rocket._
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2017-07-07 19:48:16 +02:00
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import freechips.rocketchip.util._
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2012-03-25 00:56:59 +01:00
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2017-02-09 22:59:09 +01:00
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case class RocketTileParams(
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core: RocketCoreParams = RocketCoreParams(),
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icache: Option[ICacheParams] = Some(ICacheParams()),
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dcache: Option[DCacheParams] = Some(DCacheParams()),
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rocc: Seq[RoCCParams] = Nil,
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btb: Option[BTBParams] = Some(BTBParams()),
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2017-08-01 00:40:54 +02:00
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dataScratchpadBytes: Int = 0,
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2017-09-20 07:59:28 +02:00
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trace: Boolean = false,
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2017-09-21 03:53:44 +02:00
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hcfOnUncorrectable: Boolean = false,
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2017-08-31 02:57:52 +02:00
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name: Option[String] = Some("tile"),
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2017-12-21 02:18:38 +01:00
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hartId: Int = 0,
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2017-11-18 02:26:48 +01:00
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blockerCtrlAddr: Option[BigInt] = None,
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2017-10-26 22:52:34 +02:00
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boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
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) extends TileParams {
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2017-02-09 22:59:09 +01:00
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require(icache.isDefined)
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require(dcache.isDefined)
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}
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2017-10-10 06:03:18 +02:00
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2017-12-28 23:00:13 +01:00
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class RocketTile(
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val rocketParams: RocketTileParams,
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crossing: CoreplexClockCrossing)
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(implicit p: Parameters) extends BaseTile(rocketParams, crossing)(p)
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2017-07-07 19:48:16 +02:00
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with HasExternalInterrupts
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2017-06-22 21:07:09 +02:00
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with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
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2017-01-17 03:24:08 +01:00
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with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
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2015-12-02 02:54:56 +01:00
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2017-01-17 03:24:08 +01:00
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nDCachePorts += 1 // core TODO dcachePorts += () => module.core.io.dmem ??
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2014-08-08 21:23:02 +02:00
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2017-12-21 02:18:38 +01:00
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val dtimProperty = scratch.map(d => Map(
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"sifive,dtim" -> d.device.asProperty)).getOrElse(Nil)
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val itimProperty = tileParams.icache.flatMap(_.itimAddr.map(i => Map(
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"sifive,itim" -> frontend.icache.device.asProperty))).getOrElse(Nil)
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2017-03-30 08:51:59 +02:00
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val cpuDevice = new Device {
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2017-12-21 02:18:38 +01:00
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def describe(resources: ResourceBindings): Description =
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toDescription(resources)("sifive,rocket0", dtimProperty ++ itimProperty)
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2017-03-30 08:51:59 +02:00
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}
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2017-03-02 01:47:10 +01:00
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ResourceBinding {
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2017-12-21 02:18:38 +01:00
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Resource(cpuDevice, "reg").bind(ResourceInt(BigInt(hartId)))
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2017-03-02 01:47:10 +01:00
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}
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2017-01-17 03:24:08 +01:00
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override lazy val module = new RocketTileModule(this)
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}
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2016-11-11 22:07:45 +01:00
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2017-01-17 03:24:08 +01:00
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class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
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2017-09-21 23:58:15 +02:00
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with CanHaltAndCatchFire {
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val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(Bool(OUTPUT))
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}
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2017-01-17 03:24:08 +01:00
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class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
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2017-06-22 21:07:09 +02:00
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with HasLazyRoCCModule
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2017-01-17 03:24:08 +01:00
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with CanHaveScratchpadModule {
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2017-02-09 22:59:09 +01:00
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val core = Module(p(BuildCore)(outer.p))
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2017-09-21 03:53:44 +02:00
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val uncorrectable = RegInit(Bool(false))
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2017-12-28 23:00:13 +01:00
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outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
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2017-11-07 01:54:21 +01:00
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outer.busErrorUnit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt }
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2017-03-30 04:14:04 +02:00
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core.io.hartid := io.hartid // Pass through the hartid
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2017-09-20 07:59:28 +02:00
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io.trace.foreach { _ := core.io.trace }
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2017-09-21 23:58:15 +02:00
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io.halt_and_catch_fire.foreach { _ := uncorrectable }
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2017-01-17 03:24:08 +01:00
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outer.frontend.module.io.cpu <> core.io.imem
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2017-09-02 02:50:54 +02:00
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outer.frontend.module.io.reset_vector := io.reset_vector
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2017-04-25 02:14:23 +02:00
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outer.frontend.module.io.hartid := io.hartid
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2017-04-27 00:54:43 +02:00
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outer.dcache.module.io.hartid := io.hartid
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2017-01-17 03:24:08 +01:00
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dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
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fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
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2017-03-24 21:00:47 +01:00
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core.io.ptw <> ptw.io.dpath
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2017-06-22 21:07:09 +02:00
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roccCore.cmd <> core.io.rocc.cmd
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roccCore.exception := core.io.rocc.exception
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core.io.rocc.resp <> roccCore.resp
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core.io.rocc.busy := roccCore.busy
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core.io.rocc.interrupt := roccCore.interrupt
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2016-11-21 21:19:33 +01:00
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2017-09-21 03:53:44 +02:00
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when(!uncorrectable) { uncorrectable :=
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List(outer.frontend.module.io.errors, outer.dcache.module.io.errors)
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.flatMap { e => e.uncorrectable.map(_.valid) }
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.reduceOption(_||_)
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.getOrElse(false.B)
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}
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2017-03-02 22:37:25 +01:00
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2017-02-09 22:59:09 +01:00
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// TODO eliminate this redundancy
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val h = dcachePorts.size
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val c = core.dcacheArbPorts
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val o = outer.nDCachePorts
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require(h == c, s"port list size was $h, core expected $c")
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require(h == o, s"port list size was $h, outer counted $o")
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2017-01-17 03:24:08 +01:00
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// TODO figure out how to move the below into their respective mix-ins
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dcacheArb.io.requestor <> dcachePorts
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2017-03-24 21:00:47 +01:00
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ptw.io.requestor <> ptwPorts
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2017-01-17 03:24:08 +01:00
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}
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