2017-10-20 03:51:22 +02:00
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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2017-10-20 07:19:19 +02:00
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import freechips.rocketchip.interrupts._
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2017-10-23 18:39:01 +02:00
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import freechips.rocketchip.util._
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/** Enumerates the three types of clock crossing between tiles and system bus */
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sealed trait CoreplexClockCrossing
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case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends CoreplexClockCrossing
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case class RationalCrossing(direction: RationalDirection = FastToSlow) extends CoreplexClockCrossing
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case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends CoreplexClockCrossing
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2017-10-20 03:51:22 +02:00
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2017-10-25 23:45:44 +02:00
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trait HasCrossingMethods extends LazyScope
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2017-10-20 03:51:22 +02:00
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{
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this: LazyModule =>
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2017-10-20 07:19:19 +02:00
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2017-10-25 23:45:44 +02:00
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// TileLink
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def crossTLSyncInOut(out: Boolean)(params: BufferParams = BufferParams.default)(implicit p: Parameters): TLNode = {
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this { LazyModule(new TLBuffer(params)).node }
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}
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def crossTLAsyncInOut(out: Boolean)(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): TLNode = {
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def sourceGen = LazyModule(new TLAsyncCrossingSource(sync))
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def sinkGen = LazyModule(new TLAsyncCrossingSink(depth, sync))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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sink.node :=? source.node
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NodeHandle(source.node, sink.node)
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}
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def crossTLRationalInOut(out: Boolean)(direction: RationalDirection)(implicit p: Parameters): TLNode = {
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def sourceGen = LazyModule(new TLRationalCrossingSource)
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def sinkGen = LazyModule(new TLRationalCrossingSink(if (out) direction else direction.flip))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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sink.node :=? source.node
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NodeHandle(source.node, sink.node)
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}
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def crossTLSyncIn (params: BufferParams = BufferParams.default)(implicit p: Parameters): TLNode = crossTLSyncInOut(false)(params)
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def crossTLSyncOut(params: BufferParams = BufferParams.default)(implicit p: Parameters): TLNode = crossTLSyncInOut(true )(params)
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def crossTLAsyncIn (depth: Int = 8, sync: Int = 3)(implicit p: Parameters): TLNode = crossTLAsyncInOut(false)(depth, sync)
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def crossTLAsyncOut(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): TLNode = crossTLAsyncInOut(true )(depth, sync)
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def crossTLRationalIn (direction: RationalDirection)(implicit p: Parameters): TLNode = crossTLRationalInOut(false)(direction)
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def crossTLRationalOut(direction: RationalDirection)(implicit p: Parameters): TLNode = crossTLRationalInOut(true )(direction)
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def crossTLIn(arg: CoreplexClockCrossing)(implicit p: Parameters): TLNode = arg match {
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case x: SynchronousCrossing => crossTLSyncIn(x.params)
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case x: AsynchronousCrossing => crossTLAsyncIn(x.depth, x.sync)
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case x: RationalCrossing => crossTLRationalIn(x.direction)
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}
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def crossTLOut(arg: CoreplexClockCrossing)(implicit p: Parameters): TLNode = arg match {
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case x: SynchronousCrossing => crossTLSyncOut(x.params)
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case x: AsynchronousCrossing => crossTLAsyncOut(x.depth, x.sync)
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case x: RationalCrossing => crossTLRationalOut(x.direction)
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}
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// Interrupts
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def crossIntSyncInOut(out: Boolean)(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
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def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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def sinkGen = LazyModule(new IntSyncCrossingSink(0))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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sink.node :=? source.node
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NodeHandle(source.node, sink.node)
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2017-10-20 03:51:22 +02:00
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}
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2017-10-20 07:19:19 +02:00
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2017-10-25 23:45:44 +02:00
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def crossIntAsyncInOut(out: Boolean)(sync: Int = 3, alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
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def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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def sinkGen = LazyModule(new IntSyncCrossingSink(sync))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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sink.node :=? source.node
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NodeHandle(source.node, sink.node)
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2017-10-20 07:19:19 +02:00
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}
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2017-10-25 23:45:44 +02:00
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def crossIntRationalInOut(out: Boolean)(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
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def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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def sinkGen = LazyModule(new IntSyncCrossingSink(1))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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sink.node :=? source.node
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NodeHandle(source.node, sink.node)
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}
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def crossIntSyncIn (alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntSyncInOut(false)(alreadyRegistered)
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def crossIntSyncOut(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntSyncInOut(true )(alreadyRegistered)
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def crossIntAsyncIn (sync: Int = 3, alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntAsyncInOut(false)(sync, alreadyRegistered)
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def crossIntAsyncOut(sync: Int = 3, alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntAsyncInOut(true )(sync, alreadyRegistered)
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def crossIntRationalIn (alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntRationalInOut(false)(alreadyRegistered)
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def crossIntRationalOut(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntRationalInOut(true )(alreadyRegistered)
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def crossIntIn(arg: CoreplexClockCrossing, alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = arg match {
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case x: SynchronousCrossing => crossIntSyncIn(alreadyRegistered)
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case x: AsynchronousCrossing => crossIntAsyncIn(x.sync, alreadyRegistered)
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case x: RationalCrossing => crossIntRationalIn(alreadyRegistered)
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}
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def crossIntOut(arg: CoreplexClockCrossing, alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = arg match {
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case x: SynchronousCrossing => crossIntSyncOut(alreadyRegistered)
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case x: AsynchronousCrossing => crossIntAsyncOut(x.sync, alreadyRegistered)
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case x: RationalCrossing => crossIntRationalOut(alreadyRegistered)
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}
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def crossIntIn (arg: CoreplexClockCrossing)(implicit p: Parameters): IntNode = crossIntIn (arg, false)
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def crossIntOut(arg: CoreplexClockCrossing)(implicit p: Parameters): IntNode = crossIntOut(arg, false)
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}
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trait HasCrossing extends HasCrossingMethods
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{
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this: LazyModule =>
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val crossing: CoreplexClockCrossing
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def crossTLIn (implicit p: Parameters): TLNode = crossTLIn (crossing)
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def crossTLOut (implicit p: Parameters): TLNode = crossTLOut (crossing)
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def crossIntIn (implicit p: Parameters): IntNode = crossIntIn (crossing)
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def crossIntOut(implicit p: Parameters): IntNode = crossIntOut(crossing)
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def crossIntIn (alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = crossIntIn (crossing, alreadyRegistered)
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def crossIntOut(alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = crossIntOut(crossing, alreadyRegistered)
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2017-10-20 03:51:22 +02:00
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}
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2017-10-25 23:45:44 +02:00
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class CrossingWrapper(val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends SimpleLazyModule with HasCrossing
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