52 lines
1.9 KiB
Scala
52 lines
1.9 KiB
Scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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trait HasCrossingHelper extends LazyScope
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{
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this: LazyModule =>
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val crossing: CoreplexClockCrossing
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def cross(x: TLCrossableNode, name: String): TLOutwardNode = {
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val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
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crossing match {
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case SynchronousCrossing(params) => {
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val buffer = this { LazyModule(new TLBuffer(params)) }
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buffer.suggestName(name + "SynchronousBuffer")
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buffer.node := x.node
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buffer.node
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}
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case RationalCrossing(direction) => {
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def sourceGen = LazyModule(new TLRationalCrossingSource)
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def sinkGen = LazyModule(new TLRationalCrossingSink(direction))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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source.suggestName(name + "RationalSource")
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sink.suggestName(name + "RationalSink")
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source.node := x.node
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sink.node := source.node
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sink.node
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}
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case AsynchronousCrossing(depth, sync) => {
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def sourceGen = this { LazyModule(new TLAsyncCrossingSource(sync)) }
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def sinkGen = LazyModule(new TLAsyncCrossingSink(depth, sync))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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source.suggestName(name + "AsynchronousSource")
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sink.suggestName(name + "AsynchronousSink")
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source.node := x.node
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sink.node := source.node
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sink.node
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}
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}
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}
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// def cross(x: IntCrossableNode, name: String): IntOutwardNode = { x.node }
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}
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class CrossingWrapper(val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends SimpleLazyModule with HasCrossingHelper
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