2017-10-20 03:51:22 +02:00
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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2017-10-20 07:19:19 +02:00
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import freechips.rocketchip.interrupts._
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2017-10-23 18:39:01 +02:00
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import freechips.rocketchip.util._
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/** Enumerates the three types of clock crossing between tiles and system bus */
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sealed trait CoreplexClockCrossing
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case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends CoreplexClockCrossing
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case class RationalCrossing(direction: RationalDirection = FastToSlow) extends CoreplexClockCrossing
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case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends CoreplexClockCrossing
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2017-10-20 03:51:22 +02:00
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trait HasCrossingHelper extends LazyScope
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{
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this: LazyModule =>
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val crossing: CoreplexClockCrossing
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def cross(x: TLCrossableNode): TLOutwardNode = {
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val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
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crossing match {
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case SynchronousCrossing(params) => {
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this { TLBuffer(params)(x.node) }
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}
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case RationalCrossing(direction) => {
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def sourceGen = LazyModule(new TLRationalCrossingSource)
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def sinkGen = LazyModule(new TLRationalCrossingSink(direction))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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2017-10-23 18:39:01 +02:00
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source.node :=? x.node
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sink.node :=? source.node
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2017-10-20 03:51:22 +02:00
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sink.node
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}
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case AsynchronousCrossing(depth, sync) => {
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def sourceGen = LazyModule(new TLAsyncCrossingSource(sync))
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def sinkGen = LazyModule(new TLAsyncCrossingSink(depth, sync))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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2017-10-23 18:39:01 +02:00
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source.node :=? x.node
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sink.node :=? source.node
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2017-10-20 03:51:22 +02:00
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sink.node
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}
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}
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}
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2017-10-20 07:19:19 +02:00
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def cross(
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name: Option[String] = None,
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alreadyRegistered: Boolean = false,
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overrideCrossing: Option[CoreplexClockCrossing] = None)
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(x: IntCrossableNode): IntOutwardNode = {
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val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
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overrideCrossing.getOrElse(crossing) match {
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case SynchronousCrossing(_) => {
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def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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def sinkGen = LazyModule(new IntSyncCrossingSink(0))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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name.map(_ + "SyncSource").foreach(source.suggestName)
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name.map(_ + "SyncSink").foreach(sink.suggestName)
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source.node :=? x.node
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sink.node :=? source.node
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sink.node
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}
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case RationalCrossing(_) => {
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def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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def sinkGen = LazyModule(new IntSyncCrossingSink(1))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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2017-10-23 18:39:01 +02:00
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name.map(_ + "SyncSource").foreach(source.suggestName)
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name.map(_ + "SyncSink").foreach(sink.suggestName)
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source.node :=? x.node
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sink.node :=? source.node
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2017-10-20 07:19:19 +02:00
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sink.node
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}
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case AsynchronousCrossing(_, sync) => {
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def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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def sinkGen = LazyModule(new IntSyncCrossingSink(sync))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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2017-10-23 18:39:01 +02:00
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name.map(_ + "SyncSource").foreach(source.suggestName)
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name.map(_ + "SyncSink").foreach(sink.suggestName)
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source.node :=? x.node
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sink.node :=? source.node
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2017-10-20 07:19:19 +02:00
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sink.node
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}
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}
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}
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2017-10-20 03:51:22 +02:00
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}
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class CrossingWrapper(val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends SimpleLazyModule with HasCrossingHelper
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