riscv/freedom
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base: riscv:boot-test
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riscv:ml507 riscv:boot-test riscv:master
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compare: riscv:552553e526989681e7da3b840518b6f415117514
Branches Tags
riscv:ml507 riscv:boot-test riscv:master

6 Commits
boot-test ... 552553e526

Author SHA1 Message Date
Klemens Schölhorn
552553e526 Load 32 MiB bootimage from a 2048 sector offset (first partiton) 2018-06-13 00:34:19 +02:00
Klemens Schölhorn
ee888b8c7b Rebuild when changing the bootloader 2018-06-13 00:33:46 +02:00
Klemens Schölhorn
c812a8878f Properly set clock frequencies 2018-06-06 01:05:36 +02:00
Klemens Schölhorn
2c74ef7f03 Use correct frequency for the sd-spi interface 2018-05-19 19:04:56 +02:00
Klemens Schölhorn
c27ee2215c Print everything send over serial to the terminal 2018-05-19 19:04:11 +02:00
Klemens Schölhorn
ec4e3ec36d Use rocket config with fpu and mmu for booting linux 2018-05-19 19:00:57 +02:00
5 changed files with 14 additions and 7 deletions
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3
bootrom/sdboot/kprintf.h
View File

@ -33,6 +33,9 @@ static inline void kputc(char c)
while ((int32_t)(*tx) < 0);
*tx = c;
#endif
volatile uint32_t *term = (void *) 0x64003000; // Terminal (32 bit)
while ((int32_t)(*term) < 0);
*term = c;
}
extern void kputs(const char *);

10
bootrom/sdboot/sd.c
View File

@ -10,9 +10,13 @@
#define MAX_CORES 8
#define PAYLOAD_SIZE (16 << 11)
//#define PAYLOAD_START 0
//#define PAYLOAD_CRC7 0xE1
#define PAYLOAD_START 2048
#define PAYLOAD_CRC7 0x51
#define PAYLOAD_SIZE (16 << 12)
#define F_CLK 50000000UL
#define F_CLK 60000000UL
static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR);
@ -163,7 +167,7 @@ static int copy(void)
kprintf("LOADING ");
REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 20000000UL);
if (sd_cmd(0x52, 0, 0xE1) != 0x00) {
if (sd_cmd(0x52, PAYLOAD_START, PAYLOAD_CRC7) != 0x00) {
sd_cmd_end();
return 1;
}

2
common.mk
View File

@ -63,7 +63,7 @@ endif
verilog: $(verilog)
romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
$(romgen): $(verilog)
$(romgen): $(verilog) $(BOOTROM_DIR)
ifneq ($(BOOTROM_DIR),"")
$(MAKE) -C $(BOOTROM_DIR) romgen
mv $(BUILD_DIR)/rom.v $@

2
rocket-chip

Submodule rocket-chip updated: 6df42fc360...8710fe9561

4
src/main/scala/unleashed/u500ml507devkit/Config.scala
View File

@ -20,8 +20,9 @@ import sifive.fpgashells.devices.xilinx.xilinxml507mig._
class FreedomUML507Config extends Config(
new WithoutTLMonitors ++
new WithJtagDTM ++
new WithClockFrequency(60000000) ++ // 60 MHz
new WithNMemoryChannels(1) ++
new WithNBigCores(1) ++
new WithNSmallLinuxCores(1) ++
new BaseConfig
)
@ -45,7 +46,6 @@ class U500ML507DevKitConfig extends Config(
new U500ML507DevKitPeripherals ++
new FreedomUML507Config().alter((site,here,up) => {
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 60000000) // 60 MHz clock
case MemoryML507Key => XilinxML507MIGParams(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x10000000L)