riscv/freedom
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base: riscv:175ed051d3d3d346acf65de0814effa0dd2bd1fc
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riscv:ml507
riscv:boot-test
riscv:master
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compare: riscv:87bb3a5f24c6eb71ee18f027bd776e19aec7d3cb
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riscv:ml507
riscv:boot-test
riscv:master

2 Commits
175ed051d3 ... 87bb3a5f24

Author SHA1 Message Date
Klemens Schölhorn
87bb3a5f24 Use correct clock period and memory size in config 2018-05-14 20:10:08 +02:00
Klemens Schölhorn
a3f166d5a2 Pull in memory and terminal improvements 2018-05-14 20:09:55 +02:00
3 changed files with 4 additions and 4 deletions
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2
fpga-shells

@ -1 +1 @@
Subproject commit 12cb1c2fa553a68a0ef7b584a35416f695996575
Subproject commit b49f5cfa78df56a58a6b07c5b8d1588d950dcc68

2
sifive-blocks

@ -1 +1 @@
Subproject commit 48d8524c4aa615521c3d35c388fe2025b1b05639
Subproject commit 88f1cbe4208918b785df7f3b38c3e95cdf5e616f

4
src/main/scala/unleashed/u500ml507devkit/Config.scala
View File

@ -45,10 +45,10 @@ class U500ML507DevKitConfig extends Config(
new U500ML507DevKitPeripherals ++
new FreedomUML507Config().alter((site,here,up) => {
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 60000000) // 60 MHz clock
case MemoryML507Key => XilinxML507MIGParams(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x40000000L)
case ExtMem => up(ExtMem).copy(size = 0x10000000L)
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
idcodePartNum = 0x000, // Decided to simplify.