Reduce crossing and queue depths to save space and ease timing

src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala

@@ -44,7 +44,10 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
     // Corresponds to MIG interface with 64 bit width and a burst length of 4
     val width = 256
     val beatBytes = width/8 // 32 byte (half a cache-line, fragmented)
-    val crossing = AsynchronousCrossing(8)
+
+    val address_range = AddressRange.fromSets(c.address).head
+    require(log2Ceil(address_range.size) == 28, "Max 256MiB DIMMs supported")
+    val crossing = AsynchronousCrossing(1)
 
     val device = new MemoryDevice
     val node = TLManagerNode(
@@ -90,13 +93,18 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
         // with respect to the size and address. So we can directly forward
         // the mask, (relative) address and data to the MIG interface.
 
+        // An AddressSet is always aligned, so we don't need to subtract the
+        // base address, we can just take the lower bits. The lowest 5 bits
+        // are used for indexing the 32 byte word of the MIG.
+        val address = in.a.bits.address(27, 0) & "hFFFFFE0".U
+
         // Save the source, size and type of the requests in a queue so we
         // can synthesize the right responses in fifo order. The length also
         // determines the maximum number of in-flight requests.
-        val ack_queue = Module(new Queue(new ResponseQueueIO, 4))
+        val ack_queue = Module(new Queue(new ResponseQueueIO, 2))
 
         // Pass data directly to the controller
-        controller.io.request_addr := in.a.bits.address(27, 0) & "hFFFFFE0".U
+        controller.io.request_addr := address
         controller.io.request_type := !edge.hasData(in.a.bits)
         controller.io.request_data := in.a.bits.data
         // TL uses high to indicate valid data while mig uses low
@@ -119,7 +127,7 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
         // avoid losing any responses, this queue *must* be at least as wide
         // as the ack queue, so that we can catch all responses, even if the
         // ack queue is completely filled with read requests.
-        val response_queue = Module(new Queue(controller.io.response_data, 4))
+        val response_queue = Module(new Queue(controller.io.response_data, 2))
 
         response_queue.io.enq.bits  := controller.io.response_data
         response_queue.io.enq.valid := controller.io.response_valid