Richard Xia
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f4375c2266
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Add variable to control what program gets flashed to FPGA.
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2016-12-08 12:14:17 -08:00 |
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Wesley W. Terpstra
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e95ae8aa31
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README: our systems are untethered
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2016-12-01 14:06:37 -08:00 |
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Richard Xia
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62d4e3ee15
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Merge pull request #6 from sifive/remove-consts-vh
Remove verilog header files built from Chisel .prm file.
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2016-12-01 11:05:18 -08:00 |
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Richard Xia
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db2128b4c2
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Also remove unused .prm file from Makefile.
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2016-11-30 15:00:50 -08:00 |
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Richard Xia
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c14985f3a7
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Remove verilog header files built from Chisel .prm file.
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2016-11-30 14:30:05 -08:00 |
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Henry Styles
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275e2cd693
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Merge pull request #4 from sifive/fix_u500vc707devkit_dot_img
Update U500 VC707 Dev Kit BootROM image for SDBoot
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2016-11-29 20:38:00 -08:00 |
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Henry Styles
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9fbf40da42
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fix U500 BootROM image for SDBoot
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2016-11-29 20:32:16 -08:00 |
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Olof Kindgren
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bf34011c03
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Use public accessible URL for submodules
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2016-11-29 14:30:01 -08:00 |
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SiFive
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32556462d0
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Add submodules.
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2016-11-29 05:23:27 -08:00 |
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SiFive
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3cf8128a30
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Initial commit.
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2016-11-29 05:23:11 -08:00 |
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