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Author	SHA1	Message	Date
Richard Xia	f4375c2266	Add variable to control what program gets flashed to FPGA.	2016-12-08 12:14:17 -08:00
Richard Xia	db2128b4c2	Also remove unused .prm file from Makefile.	2016-11-30 15:00:50 -08:00
Richard Xia	c14985f3a7	Remove verilog header files built from Chisel .prm file.	2016-11-30 14:30:05 -08:00