Add terminal peripheral (in same clock domain for now)

This commit is contained in:
2018-04-30 00:53:12 +02:00
parent 1cb558d2ea
commit 97eeb7af29
5 changed files with 9 additions and 2 deletions

View File

@ -12,6 +12,7 @@ import freechips.rocketchip.tile._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.terminal._
import sifive.freedom.unleashed.u500ml507devkit.fpga._
@ -32,6 +33,8 @@ class U500ML507DevKitPeripherals extends Config((site, here, up) => {
SPIParams(rAddress = BigInt(0x64001000L)))
case PeripheryGPIOKey => List(
GPIOParams(address = BigInt(0x64002000L), width = 8))
case PeripheryTerminalKey =>
TerminalParams(address = BigInt(0x64003000L))
case PeripheryMaskROMKey => List(
MaskROMParams(address = 0x10000, name = "BootROM"))
})

View File

@ -41,6 +41,7 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
// Connect peripherals
//---------------------------------------------------------------------
connectTerminal (dut)
connectDebugJTAG(dut)
connectSPI (dut)
connectUART (dut)

View File

@ -13,6 +13,7 @@ import freechips.rocketchip.system._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.terminal._
import sifive.freedom.unleashed.u500ml507devkit.fpga._
@ -25,6 +26,7 @@ class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem
with HasPeripheryDebug
with HasSystemErrorSlave
with HasPeripheryUART
with HasPeripheryTerminal
with HasPeripherySPI
with HasPeripheryGPIO
with HasMemoryML507 {
@ -36,6 +38,7 @@ class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
with HasRTCModuleImp
with HasPeripheryDebugModuleImp
with HasPeripheryUARTModuleImp
with HasPeripheryTerminalModuleImp
with HasPeripherySPIModuleImp
with HasPeripheryGPIOModuleImp {
// Reset vector is set to the location of the mask rom