From 97eeb7af293eb18641be5ca9d9bd2b2a80b4b733 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= <klemens@schoelhorn.eu>
Date: Mon, 30 Apr 2018 00:53:12 +0200
Subject: [PATCH] Add terminal peripheral (in same clock domain for now)

---
 fpga-shells                                             | 2 +-
 sifive-blocks                                           | 2 +-
 src/main/scala/unleashed/u500ml507devkit/Config.scala   | 3 +++
 src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala | 1 +
 src/main/scala/unleashed/u500ml507devkit/System.scala   | 3 +++
 5 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/fpga-shells b/fpga-shells
index b2b19cc..9c06418 160000
--- a/fpga-shells
+++ b/fpga-shells
@@ -1 +1 @@
-Subproject commit b2b19cc82223703f72a4d98796e5cab0bd393d6d
+Subproject commit 9c06418352d41142bf91a6f5b8fa9a0aca87dddc
diff --git a/sifive-blocks b/sifive-blocks
index 7ac56c0..d7b9834 160000
--- a/sifive-blocks
+++ b/sifive-blocks
@@ -1 +1 @@
-Subproject commit 7ac56c01afed8044ab73d648a51966a7198af2c6
+Subproject commit d7b9834d96829575a84f83b48cacba7b6b3d9cbe
diff --git a/src/main/scala/unleashed/u500ml507devkit/Config.scala b/src/main/scala/unleashed/u500ml507devkit/Config.scala
index 9ba2426..7e4f5eb 100644
--- a/src/main/scala/unleashed/u500ml507devkit/Config.scala
+++ b/src/main/scala/unleashed/u500ml507devkit/Config.scala
@@ -12,6 +12,7 @@ import freechips.rocketchip.tile._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
+import sifive.blocks.devices.terminal._
 
 import sifive.freedom.unleashed.u500ml507devkit.fpga._
 
@@ -32,6 +33,8 @@ class U500ML507DevKitPeripherals extends Config((site, here, up) => {
     SPIParams(rAddress = BigInt(0x64001000L)))
   case PeripheryGPIOKey => List(
     GPIOParams(address = BigInt(0x64002000L), width = 8))
+  case PeripheryTerminalKey =>
+    TerminalParams(address = BigInt(0x64003000L))
   case PeripheryMaskROMKey => List(
     MaskROMParams(address = 0x10000, name = "BootROM"))
 })
diff --git a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
index 178e087..03d2b73 100644
--- a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
+++ b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
@@ -41,6 +41,7 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
     // Connect peripherals
     //---------------------------------------------------------------------
 
+    connectTerminal (dut)
     connectDebugJTAG(dut)
     connectSPI      (dut)
     connectUART     (dut)
diff --git a/src/main/scala/unleashed/u500ml507devkit/System.scala b/src/main/scala/unleashed/u500ml507devkit/System.scala
index bc25138..fe4316a 100644
--- a/src/main/scala/unleashed/u500ml507devkit/System.scala
+++ b/src/main/scala/unleashed/u500ml507devkit/System.scala
@@ -13,6 +13,7 @@ import freechips.rocketchip.system._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
+import sifive.blocks.devices.terminal._
 
 import sifive.freedom.unleashed.u500ml507devkit.fpga._
 
@@ -25,6 +26,7 @@ class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem
     with HasPeripheryDebug
     with HasSystemErrorSlave
     with HasPeripheryUART
+    with HasPeripheryTerminal
     with HasPeripherySPI
     with HasPeripheryGPIO
     with HasMemoryML507 {
@@ -36,6 +38,7 @@ class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
     with HasRTCModuleImp
     with HasPeripheryDebugModuleImp
     with HasPeripheryUARTModuleImp
+    with HasPeripheryTerminalModuleImp
     with HasPeripherySPIModuleImp
     with HasPeripheryGPIOModuleImp {
   // Reset vector is set to the location of the mask rom