Add terminal peripheral (in same clock domain for now)
This commit is contained in:
parent
1cb558d2ea
commit
97eeb7af29
@ -1 +1 @@
|
|||||||
Subproject commit b2b19cc82223703f72a4d98796e5cab0bd393d6d
|
Subproject commit 9c06418352d41142bf91a6f5b8fa9a0aca87dddc
|
@ -1 +1 @@
|
|||||||
Subproject commit 7ac56c01afed8044ab73d648a51966a7198af2c6
|
Subproject commit d7b9834d96829575a84f83b48cacba7b6b3d9cbe
|
@ -12,6 +12,7 @@ import freechips.rocketchip.tile._
|
|||||||
import sifive.blocks.devices.gpio._
|
import sifive.blocks.devices.gpio._
|
||||||
import sifive.blocks.devices.spi._
|
import sifive.blocks.devices.spi._
|
||||||
import sifive.blocks.devices.uart._
|
import sifive.blocks.devices.uart._
|
||||||
|
import sifive.blocks.devices.terminal._
|
||||||
|
|
||||||
import sifive.freedom.unleashed.u500ml507devkit.fpga._
|
import sifive.freedom.unleashed.u500ml507devkit.fpga._
|
||||||
|
|
||||||
@ -32,6 +33,8 @@ class U500ML507DevKitPeripherals extends Config((site, here, up) => {
|
|||||||
SPIParams(rAddress = BigInt(0x64001000L)))
|
SPIParams(rAddress = BigInt(0x64001000L)))
|
||||||
case PeripheryGPIOKey => List(
|
case PeripheryGPIOKey => List(
|
||||||
GPIOParams(address = BigInt(0x64002000L), width = 8))
|
GPIOParams(address = BigInt(0x64002000L), width = 8))
|
||||||
|
case PeripheryTerminalKey =>
|
||||||
|
TerminalParams(address = BigInt(0x64003000L))
|
||||||
case PeripheryMaskROMKey => List(
|
case PeripheryMaskROMKey => List(
|
||||||
MaskROMParams(address = 0x10000, name = "BootROM"))
|
MaskROMParams(address = 0x10000, name = "BootROM"))
|
||||||
})
|
})
|
||||||
|
@ -41,6 +41,7 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
|
|||||||
// Connect peripherals
|
// Connect peripherals
|
||||||
//---------------------------------------------------------------------
|
//---------------------------------------------------------------------
|
||||||
|
|
||||||
|
connectTerminal (dut)
|
||||||
connectDebugJTAG(dut)
|
connectDebugJTAG(dut)
|
||||||
connectSPI (dut)
|
connectSPI (dut)
|
||||||
connectUART (dut)
|
connectUART (dut)
|
||||||
|
@ -13,6 +13,7 @@ import freechips.rocketchip.system._
|
|||||||
import sifive.blocks.devices.gpio._
|
import sifive.blocks.devices.gpio._
|
||||||
import sifive.blocks.devices.spi._
|
import sifive.blocks.devices.spi._
|
||||||
import sifive.blocks.devices.uart._
|
import sifive.blocks.devices.uart._
|
||||||
|
import sifive.blocks.devices.terminal._
|
||||||
|
|
||||||
import sifive.freedom.unleashed.u500ml507devkit.fpga._
|
import sifive.freedom.unleashed.u500ml507devkit.fpga._
|
||||||
|
|
||||||
@ -25,6 +26,7 @@ class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem
|
|||||||
with HasPeripheryDebug
|
with HasPeripheryDebug
|
||||||
with HasSystemErrorSlave
|
with HasSystemErrorSlave
|
||||||
with HasPeripheryUART
|
with HasPeripheryUART
|
||||||
|
with HasPeripheryTerminal
|
||||||
with HasPeripherySPI
|
with HasPeripherySPI
|
||||||
with HasPeripheryGPIO
|
with HasPeripheryGPIO
|
||||||
with HasMemoryML507 {
|
with HasMemoryML507 {
|
||||||
@ -36,6 +38,7 @@ class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
|
|||||||
with HasRTCModuleImp
|
with HasRTCModuleImp
|
||||||
with HasPeripheryDebugModuleImp
|
with HasPeripheryDebugModuleImp
|
||||||
with HasPeripheryUARTModuleImp
|
with HasPeripheryUARTModuleImp
|
||||||
|
with HasPeripheryTerminalModuleImp
|
||||||
with HasPeripherySPIModuleImp
|
with HasPeripherySPIModuleImp
|
||||||
with HasPeripheryGPIOModuleImp {
|
with HasPeripheryGPIOModuleImp {
|
||||||
// Reset vector is set to the location of the mask rom
|
// Reset vector is set to the location of the mask rom
|
||||||
|
Loading…
Reference in New Issue
Block a user