72 lines
2.1 KiB
Scala
72 lines
2.1 KiB
Scala
// See LICENSE for license details.
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package sifive.freedom.unleashed.u500ml507devkit
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import Chisel._
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import chisel3.experimental.{withClockAndReset}
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.pinctrl.{BasePin}
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import sifive.fpgashells.shell.xilinx.vc707shell._
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import sifive.fpgashells.ip.xilinx.{IOBUF}
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//-------------------------------------------------------------------------
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// PinGen
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//-------------------------------------------------------------------------
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object PinGen {
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def apply(): BasePin = {
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new BasePin()
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}
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}
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//-------------------------------------------------------------------------
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// U500ML507DevKitFPGAChip
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//-------------------------------------------------------------------------
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class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
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extends VC707Shell
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with HasDDR3
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with HasDebugJTAG {
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//-----------------------------------------------------------------------
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// DUT
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//-----------------------------------------------------------------------
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// Connect the clock to the 50 Mhz output from the PLL
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dut_clock := clk50
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withClockAndReset(dut_clock, dut_reset) {
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val dut = Module(LazyModule(new U500ML507DevKitSystem).module)
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//---------------------------------------------------------------------
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// Connect peripherals
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//---------------------------------------------------------------------
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connectDebugJTAG(dut)
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connectSPI (dut)
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connectUART (dut)
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connectMIG (dut)
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//---------------------------------------------------------------------
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// GPIO
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//---------------------------------------------------------------------
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val gpioParams = p(PeripheryGPIOKey)
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val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0)))
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GPIOPinsFromPort(gpio_pins, dut.gpio(0))
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gpio_pins.pins.foreach { _.i.ival := Bool(false) }
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gpio_pins.pins.zipWithIndex.foreach {
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case(pin, idx) => led(idx) := pin.o.oval
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}
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// tie to zero
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for( idx <- 7 to 4 ) { led(idx) := false.B }
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}
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}
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