From 5fdadd244c661bcf511768c81c70c9583fbe1a25 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= Date: Wed, 21 Mar 2018 01:31:56 +0100 Subject: [PATCH] Add makefile and config for the ml507 board The config is based on the u500vc707devkit config. --- Makefile.u500ml507devkit | 24 +++++++ .../unleashed/u500ml507devkit/Config.scala | 54 ++++++++++++++ .../unleashed/u500ml507devkit/FPGAChip.scala | 71 +++++++++++++++++++ .../unleashed/u500ml507devkit/System.scala | 46 ++++++++++++ 4 files changed, 195 insertions(+) create mode 100644 Makefile.u500ml507devkit create mode 100644 src/main/scala/unleashed/u500ml507devkit/Config.scala create mode 100644 src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala create mode 100644 src/main/scala/unleashed/u500ml507devkit/System.scala diff --git a/Makefile.u500ml507devkit b/Makefile.u500ml507devkit new file mode 100644 index 0000000..6249b03 --- /dev/null +++ b/Makefile.u500ml507devkit @@ -0,0 +1,24 @@ +# See LICENSE for license details. +base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))) +BUILD_DIR := $(base_dir)/builds/u500ml507devkit +FPGA_DIR := $(base_dir)/fpga-shells/xilinx +MODEL := U500ML507DevKitFPGAChip +PROJECT := sifive.freedom.unleashed.u500ml507devkit +export CONFIG_PROJECT := sifive.freedom.unleashed.u500ml507devkit +export CONFIG := U500ML507DevKitConfig +export BOARD := ml507 +export BOOTROM_DIR := $(base_dir)/bootrom/sdboot + +rocketchip_dir := $(base_dir)/rocket-chip +sifiveblocks_dir := $(base_dir)/sifive-blocks +VSRCS := \ + $(rocketchip_dir)/vsrc/AsyncResetReg.v \ + $(rocketchip_dir)/vsrc/plusarg_reader.v \ + $(sifiveblocks_dir)/vsrc/SRLatch.v \ + $(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \ + $(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \ + $(FPGA_DIR)/$(BOARD)/vsrc/ml507reset.v \ + $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \ + $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v + +include common.mk diff --git a/src/main/scala/unleashed/u500ml507devkit/Config.scala b/src/main/scala/unleashed/u500ml507devkit/Config.scala new file mode 100644 index 0000000..4d65d2a --- /dev/null +++ b/src/main/scala/unleashed/u500ml507devkit/Config.scala @@ -0,0 +1,54 @@ +// See LICENSE for license details. +package sifive.freedom.unleashed.u500ml507devkit + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.system._ +import freechips.rocketchip.tile._ + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.uart._ + +import sifive.fpgashells.devices.xilinx.xilinxvc707mig.{MemoryXilinxDDRKey,XilinxVC707MIGParams} + +// Default FreedomUML507Config +class FreedomUML507Config extends Config( + new WithJtagDTM ++ + new WithNMemoryChannels(1) ++ + new WithNBigCores(4) ++ + new BaseConfig +) + +// Freedom U500 ML507 Dev Kit Peripherals +class U500ML507DevKitPeripherals extends Config((site, here, up) => { + case PeripheryUARTKey => List( + UARTParams(address = BigInt(0x64000000L))) + case PeripherySPIKey => List( + SPIParams(rAddress = BigInt(0x64001000L))) + case PeripheryGPIOKey => List( + GPIOParams(address = BigInt(0x64002000L), width = 4)) + case PeripheryMaskROMKey => List( + MaskROMParams(address = 0x10000, name = "BootROM")) +}) + +// Freedom U500 ML507 Dev Kit +class U500ML507DevKitConfig extends Config( + new WithNExtTopInterrupts(0) ++ + new U500ML507DevKitPeripherals ++ + new FreedomUML507Config().alter((site,here,up) => { + case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery + case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB + case DTSTimebase => BigInt(1000000) + case ExtMem => up(ExtMem).copy(size = 0x40000000L) + case JtagDTMKey => new JtagDTMConfig ( + idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai). + idcodePartNum = 0x000, // Decided to simplify. + idcodeManufId = 0x489, // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses. + debugIdleCycles = 5) // Reasonable guess for synchronization + }) +) diff --git a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala new file mode 100644 index 0000000..a73fc9b --- /dev/null +++ b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala @@ -0,0 +1,71 @@ +// See LICENSE for license details. +package sifive.freedom.unleashed.u500ml507devkit + +import Chisel._ +import chisel3.experimental.{withClockAndReset} + +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy._ + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.pinctrl.{BasePin} + +import sifive.fpgashells.shell.xilinx.vc707shell._ +import sifive.fpgashells.ip.xilinx.{IOBUF} + +//------------------------------------------------------------------------- +// PinGen +//------------------------------------------------------------------------- + +object PinGen { + def apply(): BasePin = { + new BasePin() + } +} + +//------------------------------------------------------------------------- +// U500ML507DevKitFPGAChip +//------------------------------------------------------------------------- + +class U500ML507DevKitFPGAChip(implicit override val p: Parameters) + extends VC707Shell + with HasDDR3 + with HasDebugJTAG { + + //----------------------------------------------------------------------- + // DUT + //----------------------------------------------------------------------- + + // Connect the clock to the 50 Mhz output from the PLL + dut_clock := clk50 + withClockAndReset(dut_clock, dut_reset) { + val dut = Module(LazyModule(new U500ML507DevKitSystem).module) + + //--------------------------------------------------------------------- + // Connect peripherals + //--------------------------------------------------------------------- + + connectDebugJTAG(dut) + connectSPI (dut) + connectUART (dut) + connectMIG (dut) + + //--------------------------------------------------------------------- + // GPIO + //--------------------------------------------------------------------- + + val gpioParams = p(PeripheryGPIOKey) + val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0))) + + GPIOPinsFromPort(gpio_pins, dut.gpio(0)) + + gpio_pins.pins.foreach { _.i.ival := Bool(false) } + gpio_pins.pins.zipWithIndex.foreach { + case(pin, idx) => led(idx) := pin.o.oval + } + + // tie to zero + for( idx <- 7 to 4 ) { led(idx) := false.B } + } + +} diff --git a/src/main/scala/unleashed/u500ml507devkit/System.scala b/src/main/scala/unleashed/u500ml507devkit/System.scala new file mode 100644 index 0000000..00cc8c7 --- /dev/null +++ b/src/main/scala/unleashed/u500ml507devkit/System.scala @@ -0,0 +1,46 @@ +// See LICENSE for license details. +package sifive.freedom.unleashed.u500ml507devkit + +import Chisel._ + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.system._ + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.uart._ + +import sifive.fpgashells.devices.xilinx.xilinxvc707mig._ +import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._ + +//------------------------------------------------------------------------- +// U500ML507DevKitSystem +//------------------------------------------------------------------------- + +class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem + with HasPeripheryMaskROMSlave + with HasPeripheryDebug + with HasSystemErrorSlave + with HasPeripheryUART + with HasPeripherySPI + with HasPeripheryGPIO + with HasMemoryXilinxVC707MIG { + override lazy val module = new U500ML507DevKitSystemModule(this) +} + +class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L) + extends RocketSubsystemModuleImp(_outer) + with HasRTCModuleImp + with HasPeripheryDebugModuleImp + with HasPeripheryUARTModuleImp + with HasPeripherySPIModuleImp + with HasPeripheryGPIOModuleImp + with HasMemoryXilinxVC707MIGModuleImp { + // Reset vector is set to the location of the mask rom + val maskROMParams = p(PeripheryMaskROMKey) + global_reset_vector := maskROMParams(0).address.U +}