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sim: Add a "make sim" target

This allows users without hardware to simulate Linux on Spike.
ml507
Palmer Dabbelt 5 years ago
parent
commit
afe67e77ee
  1. 6
      .gitmodules
  2. 33
      Makefile
  3. 1
      riscv-fesvr
  4. 1
      riscv-isa-sim

6
.gitmodules vendored

@ -10,3 +10,9 @@ @@ -10,3 +10,9 @@
[submodule "riscv-gnu-toolchain"]
path = riscv-gnu-toolchain
url = https://github.com/riscv/riscv-gnu-toolchain.git
[submodule "riscv-isa-sim"]
path = riscv-isa-sim
url = https://github.com/riscv/riscv-isa-sim.git
[submodule "riscv-fesvr"]
path = riscv-fesvr
url = https://github.com/riscv/riscv-fesvr.git

33
Makefile

@ -30,6 +30,14 @@ bbl := $(pk_wrkdir)/bbl @@ -30,6 +30,14 @@ bbl := $(pk_wrkdir)/bbl
bin := $(wrkdir)/bbl.bin
hex := $(wrkdir)/bbl.hex
fesvr_srcdir := $(srcdir)/riscv-fesvr
fesvr_wrkdir := $(wrkdir)/riscv-fesvr
libfesvr := $(fesvr_wrkdir)/prefix/lib/libfesvr.so
spike_srcdir := $(srcdir)/riscv-isa-sim
spike_wrkdir := $(wrkdir)/riscv-isa-sim
spike := $(spike_wrkdir)/prefix/bin/spike
target := riscv64-unknown-linux-gnu
.PHONY: all
@ -91,6 +99,27 @@ $(bin): $(bbl) @@ -91,6 +99,27 @@ $(bin): $(bbl)
$(hex): $(bin)
xxd -c1 -p $< > $@
$(libfesvr): $(fesvr_srcdir)
rm -rf $(fesvr_wrkdir)
mkdir -p $(fesvr_wrkdir)
mkdir -p $(dir $@)
cd $(fesvr_wrkdir) && $</configure \
--prefix=$(dir $(abspath $(dir $@)))
$(MAKE) -C $(fesvr_wrkdir)
$(MAKE) -C $(fesvr_wrkdir) install
touch -c $@
$(spike): $(spike_srcdir) $(libfesvr)
rm -rf $(spike_wrkdir)
mkdir -p $(spike_wrkdir)
mkdir -p $(dir $@)
cd $(spike_wrkdir) && $</configure \
--prefix=$(dir $(abspath $(dir $@))) \
--with-fesvr=$(dir $(abspath $(dir $(libfesvr))))
$(MAKE) -C $(spike_wrkdir)
$(MAKE) -C $(spike_wrkdir) install
touch -c $@
.PHONY: sysroot vmlinux bbl
sysroot: $(sysroot)
vmlinux: $(vmlinux)
@ -99,3 +128,7 @@ bbl: $(bbl) @@ -99,3 +128,7 @@ bbl: $(bbl)
.PHONY: clean
clean:
rm -rf -- $(wrkdir) $(toolchain_dest)
.PHONY: sim
sim: $(spike) $(bbl)
$(spike) -p4 $(bbl)

1
riscv-fesvr

@ -0,0 +1 @@ @@ -0,0 +1 @@
Subproject commit f683e01542acf60e50774d061bcb396b628e3e67

1
riscv-isa-sim

@ -0,0 +1 @@ @@ -0,0 +1 @@
Subproject commit a327416eac285f50dcbb04e8ddf89204c66ece02
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