klemens 589e9960c0 Move XilinxML507MIGToTL and MIG into a separate clock domain

2018-05-10 00:30:23 +02:00

src/main/scala

Move XilinxML507MIGToTL and MIG into a separate clock domain

2018-05-10 00:30:23 +02:00

xilinx

prologue: support the absence of an xdc/tcl constraint file

2018-02-25 15:21:03 -08:00

.gitignore

Initial commit for fpga-shells

2017-08-16 11:23:45 -07:00

S

Description

Freedom FPGA mappings (https://github.com/sifive/fpga-shells)

682 KiB

Languages

Scala 89.5%

Tcl 7.8%

Verilog 2%

Makefile 0.7%