xilinxvc707pciex1: use new node-style API and abstract crossing (#13)
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@ -8,6 +8,7 @@ import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.coreplex.{HasCrossing,AsynchronousCrossing}
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import sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
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import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
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@ -27,40 +28,33 @@ class XilinxVC707PCIeX1IO extends Bundle
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val axi_ctl_aresetn = Bool(INPUT)
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}
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class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
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val slave = TLAsyncIdentityNode()
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val control = TLAsyncIdentityNode()
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val master = TLAsyncIdentityNode()
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val intnode = IntIdentityNode()
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class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule with HasCrossing {
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val crossing = AsynchronousCrossing(8)
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val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
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axi_to_pcie_x1.slave :=
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AXI4Buffer()(
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AXI4UserYanker()(
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AXI4Deinterleaver(p(CacheBlockBytes))(
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AXI4IdIndexer(idBits=4)(
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TLToAXI4(adapterName = Some("pcie-slave"))(
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TLAsyncCrossingSink()(
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slave))))))
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val slave: TLInwardNode =
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(axi_to_pcie_x1.slave
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:= AXI4Buffer()
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:= AXI4UserYanker()
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:= AXI4Deinterleaver(p(CacheBlockBytes))
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:= AXI4IdIndexer(idBits=4)
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:= TLToAXI4(adapterName = Some("pcie-slave")))
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axi_to_pcie_x1.control :=
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AXI4Buffer()(
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AXI4UserYanker(capMaxFlight = Some(2))(
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TLToAXI4()(
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TLFragmenter(4, p(CacheBlockBytes))(
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TLAsyncCrossingSink()(
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control)))))
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val control: TLInwardNode =
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(axi_to_pcie_x1.control
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:= AXI4Buffer()
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:= AXI4UserYanker(capMaxFlight = Some(2))
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:= TLToAXI4()
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:= TLFragmenter(4, p(CacheBlockBytes)))
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master :=
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TLAsyncCrossingSource()(
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TLWidthWidget(8)(
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AXI4ToTL()(
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AXI4UserYanker(capMaxFlight=Some(8))(
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AXI4Fragmenter()(
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axi_to_pcie_x1.master)))))
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val master: TLOutwardNode =
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(TLWidthWidget(8)
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:= AXI4ToTL()
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:= AXI4UserYanker(capMaxFlight=Some(8))
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:= AXI4Fragmenter()
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:= axi_to_pcie_x1.master)
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intnode := axi_to_pcie_x1.intnode
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val intnode: IntOutwardNode = axi_to_pcie_x1.intnode
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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@ -3,15 +3,17 @@ package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1
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import Chisel._
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import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
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import freechips.rocketchip.tilelink.{TLAsyncCrossingSource, TLAsyncCrossingSink}
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import freechips.rocketchip.interrupts.IntSyncCrossingSink
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trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus {
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val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
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sbus.fromAsyncFIFOMaster() := xilinxvc707pcie.master
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xilinxvc707pcie.slave := sbus.toAsyncFixedWidthSlaves()
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xilinxvc707pcie.control := sbus.toAsyncFixedWidthSlaves()
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ibus.fromAsync := xilinxvc707pcie.intnode
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sbus.fromSyncFIFOMaster(BufferParams.none) := xilinxvc707pcie.crossTLOut := xilinxvc707pcie.master
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xilinxvc707pcie.slave := xilinxvc707pcie.crossTLIn := sbus.toFixedWidthSlaves
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xilinxvc707pcie.control := xilinxvc707pcie.crossTLIn := sbus.toFixedWidthSlaves
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ibus.fromSync := xilinxvc707pcie.crossIntOut := xilinxvc707pcie.intnode
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}
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trait HasSystemXilinxVC707PCIeX1Bundle {
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