diff --git a/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala index 55ffb0b..e2be085 100644 --- a/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala +++ b/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala @@ -8,6 +8,7 @@ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.interrupts._ +import freechips.rocketchip.coreplex.{HasCrossing,AsynchronousCrossing} import sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial} import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2 @@ -27,40 +28,33 @@ class XilinxVC707PCIeX1IO extends Bundle val axi_ctl_aresetn = Bool(INPUT) } -class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule { - val slave = TLAsyncIdentityNode() - val control = TLAsyncIdentityNode() - val master = TLAsyncIdentityNode() - val intnode = IntIdentityNode() - +class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule with HasCrossing { + val crossing = AsynchronousCrossing(8) val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1) - axi_to_pcie_x1.slave := - AXI4Buffer()( - AXI4UserYanker()( - AXI4Deinterleaver(p(CacheBlockBytes))( - AXI4IdIndexer(idBits=4)( - TLToAXI4(adapterName = Some("pcie-slave"))( - TLAsyncCrossingSink()( - slave)))))) + val slave: TLInwardNode = + (axi_to_pcie_x1.slave + := AXI4Buffer() + := AXI4UserYanker() + := AXI4Deinterleaver(p(CacheBlockBytes)) + := AXI4IdIndexer(idBits=4) + := TLToAXI4(adapterName = Some("pcie-slave"))) - axi_to_pcie_x1.control := - AXI4Buffer()( - AXI4UserYanker(capMaxFlight = Some(2))( - TLToAXI4()( - TLFragmenter(4, p(CacheBlockBytes))( - TLAsyncCrossingSink()( - control))))) + val control: TLInwardNode = + (axi_to_pcie_x1.control + := AXI4Buffer() + := AXI4UserYanker(capMaxFlight = Some(2)) + := TLToAXI4() + := TLFragmenter(4, p(CacheBlockBytes))) - master := - TLAsyncCrossingSource()( - TLWidthWidget(8)( - AXI4ToTL()( - AXI4UserYanker(capMaxFlight=Some(8))( - AXI4Fragmenter()( - axi_to_pcie_x1.master))))) + val master: TLOutwardNode = + (TLWidthWidget(8) + := AXI4ToTL() + := AXI4UserYanker(capMaxFlight=Some(8)) + := AXI4Fragmenter() + := axi_to_pcie_x1.master) - intnode := axi_to_pcie_x1.intnode + val intnode: IntOutwardNode = axi_to_pcie_x1.intnode lazy val module = new LazyModuleImp(this) { val io = IO(new Bundle { diff --git a/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala index 2fb476f..7c7a740 100644 --- a/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala +++ b/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala @@ -3,15 +3,17 @@ package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1 import Chisel._ import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} +import freechips.rocketchip.tilelink.{TLAsyncCrossingSource, TLAsyncCrossingSink} +import freechips.rocketchip.interrupts.IntSyncCrossingSink trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus { val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) - sbus.fromAsyncFIFOMaster() := xilinxvc707pcie.master - xilinxvc707pcie.slave := sbus.toAsyncFixedWidthSlaves() - xilinxvc707pcie.control := sbus.toAsyncFixedWidthSlaves() - ibus.fromAsync := xilinxvc707pcie.intnode + sbus.fromSyncFIFOMaster(BufferParams.none) := xilinxvc707pcie.crossTLOut := xilinxvc707pcie.master + xilinxvc707pcie.slave := xilinxvc707pcie.crossTLIn := sbus.toFixedWidthSlaves + xilinxvc707pcie.control := xilinxvc707pcie.crossTLIn := sbus.toFixedWidthSlaves + ibus.fromSync := xilinxvc707pcie.crossIntOut := xilinxvc707pcie.intnode } trait HasSystemXilinxVC707PCIeX1Bundle {