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xilinxvc707pciex1: use new node-style API and abstract crossing (#13)

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This commit is contained in:
Wesley W. Terpstra
2017-10-28 12:27:24 -07:00
committed by GitHub
parent 65ac5d4588
commit df8e6b8e8c
2 changed files with 30 additions and 34 deletions
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52
src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@@ -8,6 +8,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._ import freechips.rocketchip.interrupts._
import freechips.rocketchip.coreplex.{HasCrossing,AsynchronousCrossing}
import sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial} import sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2 import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
@@ -27,40 +28,33 @@ class XilinxVC707PCIeX1IO extends Bundle
val axi_ctl_aresetn = Bool(INPUT) val axi_ctl_aresetn = Bool(INPUT)
} }
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule { class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule with HasCrossing {
val slave = TLAsyncIdentityNode() val crossing = AsynchronousCrossing(8)
val control = TLAsyncIdentityNode()
val master = TLAsyncIdentityNode()
val intnode = IntIdentityNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1) val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
axi_to_pcie_x1.slave := val slave: TLInwardNode =
AXI4Buffer()( (axi_to_pcie_x1.slave
AXI4UserYanker()( := AXI4Buffer()
AXI4Deinterleaver(p(CacheBlockBytes))( := AXI4UserYanker()
AXI4IdIndexer(idBits=4)( := AXI4Deinterleaver(p(CacheBlockBytes))
TLToAXI4(adapterName = Some("pcie-slave"))( := AXI4IdIndexer(idBits=4)
TLAsyncCrossingSink()( := TLToAXI4(adapterName = Some("pcie-slave")))
slave))))))
axi_to_pcie_x1.control := val control: TLInwardNode =
AXI4Buffer()( (axi_to_pcie_x1.control
AXI4UserYanker(capMaxFlight = Some(2))( := AXI4Buffer()
TLToAXI4()( := AXI4UserYanker(capMaxFlight = Some(2))
TLFragmenter(4, p(CacheBlockBytes))( := TLToAXI4()
TLAsyncCrossingSink()( := TLFragmenter(4, p(CacheBlockBytes)))
control)))))
master := val master: TLOutwardNode =
TLAsyncCrossingSource()( (TLWidthWidget(8)
TLWidthWidget(8)( := AXI4ToTL()
AXI4ToTL()( := AXI4UserYanker(capMaxFlight=Some(8))
AXI4UserYanker(capMaxFlight=Some(8))( := AXI4Fragmenter()
AXI4Fragmenter()( := axi_to_pcie_x1.master)
axi_to_pcie_x1.master)))))
intnode := axi_to_pcie_x1.intnode val intnode: IntOutwardNode = axi_to_pcie_x1.intnode
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle { val io = IO(new Bundle {

12
src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
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@@ -3,15 +3,17 @@ package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1
import Chisel._ import Chisel._
import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus} import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
import freechips.rocketchip.tilelink.{TLAsyncCrossingSource, TLAsyncCrossingSink}
import freechips.rocketchip.interrupts.IntSyncCrossingSink
trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus { trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
sbus.fromAsyncFIFOMaster() := xilinxvc707pcie.master sbus.fromSyncFIFOMaster(BufferParams.none) := xilinxvc707pcie.crossTLOut := xilinxvc707pcie.master
xilinxvc707pcie.slave := sbus.toAsyncFixedWidthSlaves() xilinxvc707pcie.slave := xilinxvc707pcie.crossTLIn := sbus.toFixedWidthSlaves
xilinxvc707pcie.control := sbus.toAsyncFixedWidthSlaves() xilinxvc707pcie.control := xilinxvc707pcie.crossTLIn := sbus.toFixedWidthSlaves
ibus.fromAsync := xilinxvc707pcie.intnode ibus.fromSync := xilinxvc707pcie.crossIntOut := xilinxvc707pcie.intnode
} }
trait HasSystemXilinxVC707PCIeX1Bundle { trait HasSystemXilinxVC707PCIeX1Bundle {