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fix PCIe vc707 design contraints : PCIe pins and UART RX sync register

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This commit is contained in:
Henry Styles 2017-09-07 10:41:12 -07:00
parent 2389e6e957
commit b7ee0ab0f0
1 changed files with 5 additions and 5 deletions
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10
xilinx/vc707/constraints/vc707-master.xdc
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@ -31,7 +31,7 @@ set_property IOB TRUE [get_ports uart_rtsn]
# Platform specific constraints
set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"]
set_property IOB TRUE [get_cells "uart_rx_sync_0"]
set_property IOB TRUE [get_cells "uart_rx_sync_0_reg"]
# PCI Express
#FMC 1 refclk
@ -40,11 +40,11 @@ set_property PACKAGE_PIN A9 [get_ports {pci_exp_refclk_rxn}]
create_clock -name pcie_ref_clk -period 10 [get_ports pci_exp_refclk_rxp]
set_input_jitter [get_clocks -of_objects [get_ports pci_exp_refclk_rxp]] 0.5
set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp[0]}]
set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn[0]}]
set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp}]
set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn}]
set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp[0]}]
set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn[0]}]
set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp}]
set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn}]
# JTAG
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]