diff --git a/xilinx/vc707/constraints/vc707-master.xdc b/xilinx/vc707/constraints/vc707-master.xdc
index 608a358..ff1fea3 100644
--- a/xilinx/vc707/constraints/vc707-master.xdc
+++ b/xilinx/vc707/constraints/vc707-master.xdc
@@ -31,7 +31,7 @@ set_property IOB TRUE [get_ports uart_rtsn]
 
 # Platform specific constraints
 set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"]
-set_property IOB TRUE [get_cells "uart_rx_sync_0"]
+set_property IOB TRUE [get_cells "uart_rx_sync_0_reg"]
 
 # PCI Express
 #FMC 1 refclk
@@ -40,11 +40,11 @@ set_property PACKAGE_PIN A9 [get_ports {pci_exp_refclk_rxn}]
 create_clock -name pcie_ref_clk -period 10 [get_ports pci_exp_refclk_rxp]
 set_input_jitter [get_clocks -of_objects [get_ports pci_exp_refclk_rxp]] 0.5
 
-set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp[0]}]
-set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn[0]}]
+set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp}]
+set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn}]
 
-set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp[0]}]
-set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn[0]}]
+set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp}]
+set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn}]
 
 # JTAG
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]