Initial commit for fpga-shells

xilinx/common/tcl/bitstream.tcl

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+# See LICENSE for license details.
+
+# Write a bitstream for the current design
+write_bitstream -force [file join $wrkdir "${top}.bit"]
+
+# Save the timing delays for cells in the design in SDF format
+write_sdf -force [file join $wrkdir "${top}.sdf"]
+
+# Export the current netlist in verilog format
+write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]

xilinx/common/tcl/boards.tcl

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+# See LICENSE for license details.
+
+namespace eval ::program::boards {}
+
+set ::program::boards::spec [dict create \
+	arty            [dict create  iface spix4   size 16   bitaddr 0x0        memdev {n25q128-3.3v-spi-x1_x2_x4}] \
+	vc707           [dict create  iface bpix16  size 128  bitaddr 0x3000000  ]]

xilinx/common/tcl/init.tcl

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+# See LICENSE for license details.
+
+# Include helper functions
+source [file join $scriptdir "util.tcl"]
+
+# Create the diretory for IPs
+file mkdir $ipdir
+
+# Update the IP catalog
+update_ip_catalog -rebuild
+
+# Board specific IP implementation
+source [file join $boarddir tcl ip.tcl]
+
+# AR 58526 <http://www.xilinx.com/support/answers/58526.html>
+set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
+
+# Get a list of IPs in the current design
+set obj [get_ips]
+
+# Generate target data for the inlcuded IPs in the design
+generate_target all $obj
+
+# Export the IP user files
+export_ip_user_files -of_objects $obj -no_script -force
+
+# Get the list of active source and constraint files
+set obj [current_fileset]
+
+#Xilinx bug workaround
+#scrape IP tree for directories containing .vh files
+#[get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
+set property_include_dirs [get_property include_dirs $obj]
+
+# Include generated files for the IPs in the design
+set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
+set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
+set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]

xilinx/common/tcl/opt.tcl

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+# See LICENSE for license details.
+
+# Optimize the netlist
+opt_design -directive Explore
+
+# Checkpoint the current design
+write_checkpoint -force [file join $wrkdir post_opt]

xilinx/common/tcl/place.tcl

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+# See LICENSE for license details.
+
+# Place the current design
+place_design -directive Explore
+
+# Optimize the current placed netlist
+phys_opt_design -directive Explore
+
+# Optimize dynamic power using intelligent clock gating
+power_opt_design
+
+# Checkpoint the current design
+write_checkpoint -force [file join $wrkdir post_place]

xilinx/common/tcl/post-impl-debug.tcl

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+# See LICENSE for license details.
+
+# Write debug probes, save MMI for BRAMs in the design

xilinx/common/tcl/pre-impl-debug.tcl

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+# See LICENSE for license details.
+
+# Instantiate ILAs

xilinx/common/tcl/prologue.tcl

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+# See LICENSE for license details.
+
+# Set the variable for the directory that includes all scripts
+set scriptdir [file dirname [info script]]
+
+# Set the variable for all the common files
+set commondir [file dirname $scriptdir]
+
+# Set the variable that points to board specific files
+set boarddir [file join [file dirname $commondir] $name]
+
+# Set the variable that points to board constraint files
+set constraintsdir [file join $boarddir constraints]
+
+# Set the variable that points to common verilog sources
+set srcdir [file join $commondir vsrc]
+
+# Creates a work directory
+set wrkdir [file join [pwd] obj]
+
+# Create the directory for IPs
+set ipdir [file join $wrkdir ip]
+
+# Set the top for the design based on an environment variable
+set top $::env(FPGA_TOP_SYSTEM)
+
+# Create an in-memory project
+create_project -part $part_fpga -in_memory
+
+# Set the board part, target language, default library, and IP directory
+# paths for the current project
+set_property -dict [list \
+	BOARD_PART $part_board \
+	TARGET_LANGUAGE {Verilog} \
+	DEFAULT_LIB {xil_defaultlib} \
+	IP_REPO_PATHS $ipdir \
+	] [current_project]
+
+if {[get_filesets -quiet sources_1] eq ""} {
+	create_fileset -srcset sources_1
+}
+set obj [current_fileset]
+
+# Add verilog files from VSRCS environment variable
+if {[info exists ::env(VSRCS)]} {
+  # Split string into words even with multiple consecutive spaces
+  # http://wiki.tcl.tk/989
+  set vsrcs [regexp -inline -all -- {\S+} $::env(VSRCS)]
+  foreach vsrc $vsrcs {
+    add_files -norecurse -fileset $obj $vsrc
+  }
+}
+
+if {[get_filesets -quiet sim_1] eq ""} {
+	create_fileset -simset sim_1
+}
+set obj [current_fileset -simset]
+
+if {[get_filesets -quiet constrs_1] eq ""} {
+	create_fileset -constrset constrs_1
+}
+
+set obj [current_fileset -constrset]
+add_files -norecurse -fileset $obj [glob -directory $constraintsdir {*.xdc}]

xilinx/common/tcl/report.tcl

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+# See LICENSE for license details.
+
+# Create a report directory
+set rptdir [file join $wrkdir report]
+file mkdir $rptdir
+
+# Create a datasheet for the current design
+report_datasheet -file [file join $rptdir datasheet.txt]
+
+# Report utilization of the current device
+set rptutil [file join $rptdir utilization.txt]
+report_utilization -hierarchical -file $rptutil
+
+# Report information about clock nets in the design
+report_clock_utilization -file $rptutil -append
+
+# Report the RAM resources utilized in the implemented design
+report_ram_utilization -file $rptutil -append -detail
+
+# Report timing summary for a max of 10 paths per group
+report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
+
+# Report the highest fanout of nets in the implemented design
+report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
+
+# Run DRC
+report_drc -file [file join $rptdir drc.txt]
+
+# Report details of the IO banks in the design
+report_io -file [file join $rptdir io.txt]
+
+# Report a table of all clocks in the design
+report_clocks -file [file join $rptdir clocks.txt]
+
+# Fail loudly if timing not met
+#
+# We would ideally elevate critical warning Route 35-39 to an error, but it is
+# currently not being emitted with our flow for some reason.
+# https://forums.xilinx.com/t5/Implementation/Making-timing-violations-fatal-to-the-Vivado-build/m-p/716957#M15979
+set timing_slack [get_property SLACK [get_timing_paths]]
+if {$timing_slack < 0} {
+  puts "Failed to meet timing by $timing_slack, see [file join $rptdir timing.txt]"
+  exit 1
+}

xilinx/common/tcl/route.tcl

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+# See LICENSE for license details.
+
+# Route the current design
+route_design -directive Explore
+
+# Optimize the current design post routing
+phys_opt_design -directive Explore
+
+# Checkpoint the current design
+write_checkpoint -force [file join $wrkdir post_route]

xilinx/common/tcl/synth.tcl

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+# See LICENSE for license details.
+
+# Read the specified list of IP files
+read_ip [glob -directory $ipdir [file join * {*.xci}]]
+
+# Synthesize the design
+synth_design -top $top -flatten_hierarchy rebuilt
+
+# Checkpoint the current design
+write_checkpoint -force [file join $wrkdir post_synth]

xilinx/common/tcl/util.tcl

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+# See LICENSE for license details.
+
+# Helper function that recursively includes files given a directory and a
+# pattern/suffix extensions
+proc recglob { basedir pattern } {
+  set dirlist [glob -nocomplain -directory $basedir -type d *]
+  set findlist [glob -nocomplain -directory $basedir $pattern]
+  foreach dir $dirlist {
+    set reclist [recglob $dir $pattern]
+    set findlist [concat $findlist $reclist]
+  }
+  return $findlist
+}
+
+# Helper function to find all subdirectories containing ".vh" files
+proc findincludedir { basedir pattern } {
+  set vhfiles [recglob $basedir $pattern]
+  set vhdirs {}
+  foreach match $vhfiles {
+    lappend vhdirs [file dir $match]
+  }
+  set uniquevhdirs [lsort -unique $vhdirs]
+  return $uniquevhdirs
+}

xilinx/common/tcl/vivado.tcl

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+# See LICENSE for license details.
+
+# Synthesize the design
+source [file join $scriptdir "synth.tcl"]
+
+# Pre-implementation debug
+source [file join $scriptdir "pre-impl-debug.tcl"]
+
+# Post synthesis optimization
+source [file join $scriptdir "opt.tcl"]
+
+# Place the design
+source [file join $scriptdir "place.tcl"]
+
+# Route the design
+source [file join $scriptdir "route.tcl"]
+
+# Generate bitstream and save verilog netlist
+source [file join $scriptdir "bitstream.tcl"]
+
+# Post-implementation debug
+source [file join $scriptdir "post-impl-debug.tcl"]
+
+# Create reports for the current implementation
+source [file join $scriptdir "report.tcl"]

xilinx/common/tcl/write_cfgmem.tcl

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+# See LICENSE for license details.
+#
+# Create an MCS-format memory configuration file from a bitstream and an
+# optional data file.
+
+set script_program_dir [file dirname [info script]]
+source [file join $script_program_dir {boards.tcl}]
+
+if {$argc < 3 || $argc > 4} {
+	puts $argc
+	puts {Error: Invalid number of arguments}
+	puts {Usage: write_cfgmem.tcl board mcsfile bitfile [datafile]}
+	exit 1
+}
+lassign $argv board mcsfile bitfile datafile
+
+if {![dict exists $::program::boards::spec $board]} {
+	puts {Unsupported board}
+	exit 1
+}
+set board [dict get $::program::boards::spec $board]
+
+write_cfgmem -format mcs -interface [dict get $board iface] -size [dict get $board size] \
+	-loadbit "up [dict get $board bitaddr] $bitfile" \
+	-loaddata [expr {$datafile ne "" ? "up 0x400000 $datafile" : ""}] \
+	-file $mcsfile -force