11 lines
365 B
Tcl
11 lines
365 B
Tcl
# See LICENSE for license details.
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# Write a bitstream for the current design
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write_bitstream -force [file join $wrkdir "${top}.bit"]
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# Save the timing delays for cells in the design in SDF format
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write_sdf -force [file join $wrkdir "${top}.sdf"]
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# Export the current netlist in verilog format
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write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]
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