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Initial commit for fpga-shells

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This commit is contained in:
Shreesha Srinath
2017-08-16 11:23:45 -07:00
commit ab8cf0775f
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157
src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala Normal file
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// See LICENSE for license details.
package sifive.fpgashells.devices.xilinx.xilinxvc707mig
import Chisel._
import chisel3.experimental.{Analog,attach}
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
trait HasXilinxVC707MIGParameters {
}
class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR
class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR
with VC707MIGIOClocksReset
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
val device = new MemoryDevice
val node = TLInputNode()
val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
resources = device.reg,
regionType = RegionType.UNCACHED,
executable = true,
supportsWrite = TransferSizes(1, 256*8),
supportsRead = TransferSizes(1, 256*8))),
beatBytes = 8)))
val xing = LazyModule(new TLAsyncCrossing)
val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
val yank = LazyModule(new AXI4UserYanker)
val buffer = LazyModule(new AXI4Buffer)
xing.node := node
val monitor = (toaxi4.node := xing.node)
axi4 := buffer.node
buffer.node := yank.node
yank.node := deint.node
deint.node := indexer.node
indexer.node := toaxi4.node
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val port = new XilinxVC707MIGIO
val tl = node.bundleIn
}
//MIG black box instantiation
val blackbox = Module(new vc707mig)
//pins to top level
//inouts
attach(io.port.ddr3_dq,blackbox.io.ddr3_dq)
attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n)
attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p)
//outputs
io.port.ddr3_addr := blackbox.io.ddr3_addr
io.port.ddr3_ba := blackbox.io.ddr3_ba
io.port.ddr3_ras_n := blackbox.io.ddr3_ras_n
io.port.ddr3_cas_n := blackbox.io.ddr3_cas_n
io.port.ddr3_we_n := blackbox.io.ddr3_we_n
io.port.ddr3_reset_n := blackbox.io.ddr3_reset_n
io.port.ddr3_ck_p := blackbox.io.ddr3_ck_p
io.port.ddr3_ck_n := blackbox.io.ddr3_ck_n
io.port.ddr3_cke := blackbox.io.ddr3_cke
io.port.ddr3_cs_n := blackbox.io.ddr3_cs_n
io.port.ddr3_dm := blackbox.io.ddr3_dm
io.port.ddr3_odt := blackbox.io.ddr3_odt
//inputs
//NO_BUFFER clock
blackbox.io.sys_clk_i := io.port.sys_clk_i
//user interface signals
val axi_async = axi4.bundleIn(0)
xing.module.io.in_clock := clock
xing.module.io.in_reset := reset
xing.module.io.out_clock := blackbox.io.ui_clk
xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
(Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
lm.module.clock := blackbox.io.ui_clk
lm.module.reset := blackbox.io.ui_clk_sync_rst
}
io.port.ui_clk := blackbox.io.ui_clk
io.port.ui_clk_sync_rst := blackbox.io.ui_clk_sync_rst
io.port.mmcm_locked := blackbox.io.mmcm_locked
blackbox.io.aresetn := io.port.aresetn
blackbox.io.app_sr_req := Bool(false)
blackbox.io.app_ref_req := Bool(false)
blackbox.io.app_zq_req := Bool(false)
//app_sr_active := unconnected
//app_ref_ack := unconnected
//app_zq_ack := unconnected
//slave AXI interface write address ports
blackbox.io.s_axi_awid := axi_async.aw.bits.id
blackbox.io.s_axi_awaddr := axi_async.aw.bits.addr //truncation ??
blackbox.io.s_axi_awlen := axi_async.aw.bits.len
blackbox.io.s_axi_awsize := axi_async.aw.bits.size
blackbox.io.s_axi_awburst := axi_async.aw.bits.burst
blackbox.io.s_axi_awlock := axi_async.aw.bits.lock
blackbox.io.s_axi_awcache := UInt("b0011")
blackbox.io.s_axi_awprot := axi_async.aw.bits.prot
blackbox.io.s_axi_awqos := axi_async.aw.bits.qos
blackbox.io.s_axi_awvalid := axi_async.aw.valid
axi_async.aw.ready := blackbox.io.s_axi_awready
//slave interface write data ports
blackbox.io.s_axi_wdata := axi_async.w.bits.data
blackbox.io.s_axi_wstrb := axi_async.w.bits.strb
blackbox.io.s_axi_wlast := axi_async.w.bits.last
blackbox.io.s_axi_wvalid := axi_async.w.valid
axi_async.w.ready := blackbox.io.s_axi_wready
//slave interface write response
blackbox.io.s_axi_bready := axi_async.b.ready
axi_async.b.bits.id := blackbox.io.s_axi_bid
axi_async.b.bits.resp := blackbox.io.s_axi_bresp
axi_async.b.valid := blackbox.io.s_axi_bvalid
//slave AXI interface read address ports
blackbox.io.s_axi_arid := axi_async.ar.bits.id
blackbox.io.s_axi_araddr := axi_async.ar.bits.addr //truncation ??
blackbox.io.s_axi_arlen := axi_async.ar.bits.len
blackbox.io.s_axi_arsize := axi_async.ar.bits.size
blackbox.io.s_axi_arburst := axi_async.ar.bits.burst
blackbox.io.s_axi_arlock := axi_async.ar.bits.lock
blackbox.io.s_axi_arcache := UInt("b0011")
blackbox.io.s_axi_arprot := axi_async.ar.bits.prot
blackbox.io.s_axi_arqos := axi_async.ar.bits.qos
blackbox.io.s_axi_arvalid := axi_async.ar.valid
axi_async.ar.ready := blackbox.io.s_axi_arready
//slace AXI interface read data ports
blackbox.io.s_axi_rready := axi_async.r.ready
axi_async.r.bits.id := blackbox.io.s_axi_rid
axi_async.r.bits.data := blackbox.io.s_axi_rdata
axi_async.r.bits.resp := blackbox.io.s_axi_rresp
axi_async.r.bits.last := blackbox.io.s_axi_rlast
axi_async.r.valid := blackbox.io.s_axi_rvalid
//misc
io.port.init_calib_complete := blackbox.io.init_calib_complete
blackbox.io.sys_rst :=io.port.sys_rst
//mig.device_temp :- unconnceted
}
}

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src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala Normal file
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// See LICENSE for license details.
package sifive.fpgashells.devices.xilinx.xilinxvc707mig
import Chisel._
import freechips.rocketchip.coreplex.HasMemoryBus
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
val module: HasMemoryXilinxVC707MIGModuleImp
val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
xilinxvc707mig.node := memBuses.head.toDRAMController
}
trait HasMemoryXilinxVC707MIGBundle {
val xilinxvc707mig: XilinxVC707MIGIO
def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
pads <> xilinxvc707mig
}
}
trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
with HasMemoryXilinxVC707MIGBundle {
val outer: HasMemoryXilinxVC707MIG
val xilinxvc707mig = IO(new XilinxVC707MIGIO)
xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
}

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src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala Normal file
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// See LICENSE for license details.
package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1
import Chisel._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
class XilinxVC707PCIeX1Pads extends Bundle with VC707AXIToPCIeX1IOSerial
class XilinxVC707PCIeX1IO extends Bundle
with VC707AXIToPCIeX1IOSerial
with VC707AXIToPCIeX1IOClocksReset {
val axi_ctl_aresetn = Bool(INPUT)
val REFCLK_rxp = Bool(INPUT)
val REFCLK_rxn = Bool(INPUT)
}
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
val slave = TLAsyncInputNode()
val control = TLAsyncInputNode()
val master = TLAsyncOutputNode()
val intnode = IntOutputNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
axi_to_pcie_x1.slave :=
AXI4Buffer()(
AXI4UserYanker()(
AXI4Deinterleaver(p(CacheBlockBytes))(
AXI4IdIndexer(idBits=4)(
TLToAXI4(beatBytes=8, adapterName = Some("pcie-slave"))(
TLAsyncCrossingSink()(
slave))))))
axi_to_pcie_x1.control :=
AXI4Buffer()(
AXI4UserYanker(capMaxFlight = Some(2))(
TLToAXI4(beatBytes=4)(
TLFragmenter(4, p(CacheBlockBytes))(
TLAsyncCrossingSink()(
control)))))
master :=
TLAsyncCrossingSource()(
TLWidthWidget(8)(
AXI4ToTL()(
AXI4UserYanker(capMaxFlight=Some(8))(
AXI4Fragmenter()(
axi_to_pcie_x1.master)))))
intnode := axi_to_pcie_x1.intnode
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val port = new XilinxVC707PCIeX1IO
val slave_in = slave.bundleIn
val control_in = control.bundleIn
val master_out = master.bundleOut
val interrupt = intnode.bundleOut
}
io.port <> axi_to_pcie_x1.module.io.port
//PCIe Reference Clock
val ibufds_gte2 = Module(new IBUFDS_GTE2)
axi_to_pcie_x1.module.io.REFCLK := ibufds_gte2.io.O
ibufds_gte2.io.CEB := UInt(0)
ibufds_gte2.io.I := io.port.REFCLK_rxp
ibufds_gte2.io.IB := io.port.REFCLK_rxn
}
}

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src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala Normal file
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// See LICENSE for license details.
package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1
import Chisel._
import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
sbus.fromAsyncFIFOMaster() := xilinxvc707pcie.master
xilinxvc707pcie.slave := sbus.toAsyncFixedWidthSlaves()
xilinxvc707pcie.control := sbus.toAsyncFixedWidthSlaves()
ibus.fromAsync := xilinxvc707pcie.intnode
}
trait HasSystemXilinxVC707PCIeX1Bundle {
val xilinxvc707pcie: XilinxVC707PCIeX1IO
def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
pads <> xilinxvc707pcie
}
}
trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
with HasSystemXilinxVC707PCIeX1Bundle {
val outer: HasSystemXilinxVC707PCIeX1
val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
outer.xilinxvc707pcie.module.reset := ~xilinxvc707pcie.axi_aresetn
}

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src/main/scala/ip/xilinx/Xilinx.scala Normal file
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// See LICENSE for license details.
package sifive.fpgashells.ip.xilinx
import Chisel._
import chisel3.core.{Input, Output, attach}
import chisel3.experimental.{Analog}
import sifive.blocks.devices.pinctrl.{BasePin}
//========================================================================
// This file contains common devices used by our Xilinx FPGA flows and some
// BlackBox modules used in the Xilinx FPGA flows
//========================================================================
//-------------------------------------------------------------------------
// IBUFDS
//-------------------------------------------------------------------------
//IP : xilinx unisim IBUFDS. SelectIO Differential Signaling Input
// Buffer unparameterized
class IBUFDS extends BlackBox {
val io = new Bundle {
val O = Bool(OUTPUT)
val I = Bool(INPUT)
val IB = Bool(INPUT)
}
}
//-------------------------------------------------------------------------
// IBUFG
//-------------------------------------------------------------------------
/** IBUFG -- Clock Input Buffer */
class IBUFG extends BlackBox {
val io = new Bundle {
val O = Output(Clock())
val I = Input(Clock())
}
}
object IBUFG {
def apply (pin: Clock): Clock = {
val pad = Module (new IBUFG())
pad.io.I := pin
pad.io.O
}
}
//-------------------------------------------------------------------------
// IOBUF
//-------------------------------------------------------------------------
/** IOBUF -- Bidirectional IO Buffer. */
class IOBUF extends BlackBox {
val io = new Bundle {
val O = Output(Bool())
val IO = Analog(1.W)
val I = Input(Bool())
val T = Input(Bool())
}
}
object IOBUF {
def apply (pin: Analog, ctrl: BasePin): Bool = {
val pad = Module(new IOBUF())
pad.io.I := ctrl.o.oval
pad.io.T := ~ctrl.o.oe
ctrl.i.ival := pad.io.O & ctrl.o.ie
attach(pad.io.IO, pin)
pad.io.O & ctrl.o.ie
}
// Creates an output IOBUF
def apply (pin: Analog, in: Bool): Unit = {
val pad = Module(new IOBUF())
pad.io.I := in
pad.io.T := false.B
attach(pad.io.IO, pin)
}
// Creates an input IOBUF
def apply (pin: Analog): Bool = {
val pad = Module(new IOBUF())
pad.io.I := false.B
pad.io.T := true.B
attach(pad.io.IO, pin)
pad.io.O
}
}
//-------------------------------------------------------------------------
// PULLUP
//-------------------------------------------------------------------------
/** PULLUP : can be applied to Input to add a Pullup. */
class PULLUP extends BlackBox {
val io = new Bundle {
val O = Analog(1.W)
}
}
object PULLUP {
def apply (pin: Analog): Unit = {
val pullup = Module(new PULLUP())
attach(pullup.io.O, pin)
}
}
//-------------------------------------------------------------------------
// mmcm
//-------------------------------------------------------------------------
/** mmcm: This is generated by the Xilinx IP Generation Scripts */
class mmcm extends BlackBox {
val io = new Bundle {
val clk_in1 = Input(Clock())
val clk_out1 = Output(Clock())
val clk_out2 = Output(Clock())
val clk_out3 = Output(Clock())
val resetn = Input(Bool())
val locked = Output(Bool())
}
}
//-------------------------------------------------------------------------
// reset_sys
//-------------------------------------------------------------------------
/** reset_sys: This is generated by the Xilinx IP Generation Scripts */
class reset_sys extends BlackBox {
val io = new Bundle {
val slowest_sync_clk = Input(Clock())
val ext_reset_in = Input(Bool())
val aux_reset_in = Input(Bool())
val mb_debug_sys_rst = Input(Bool())
val dcm_locked = Input(Bool())
val mb_reset = Output(Bool())
val bus_struct_reset = Output(Bool())
val peripheral_reset = Output(Bool())
val interconnect_aresetn = Output(Bool())
val peripheral_aresetn = Output(Bool())
}
}
//-------------------------------------------------------------------------
// reset_mig
//-------------------------------------------------------------------------
/** reset_mig: This is generated by the Xilinx IP Generation Scripts */
class reset_mig extends BlackBox {
val io = new Bundle {
val slowest_sync_clk = Input(Clock())
val ext_reset_in = Input(Bool())
val aux_reset_in = Input(Bool())
val mb_debug_sys_rst = Input(Bool())
val dcm_locked = Input(Bool())
val mb_reset = Output(Bool())
val bus_struct_reset = Output(Bool())
val peripheral_reset = Output(Bool())
val interconnect_aresetn = Output(Bool())
val peripheral_aresetn = Output(Bool())
}
}
//-------------------------------------------------------------------------
// PowerOnResetFPGAOnly
//-------------------------------------------------------------------------
/** PowerOnResetFPGAOnly -- this generates a power_on_reset signal using
* initial blocks. It is synthesizable on FPGA flows only.
*/
// This is a FPGA-Only construct, which uses
// 'initial' constructions
class PowerOnResetFPGAOnly extends BlackBox {
val io = new Bundle {
val clock = Input(Clock())
val power_on_reset = Output(Bool())
}
}
object PowerOnResetFPGAOnly {
def apply (clk: Clock): Bool = {
val por = Module(new PowerOnResetFPGAOnly())
por.io.clock := clk
por.io.power_on_reset
}
}
//-------------------------------------------------------------------------
// vc707clk_wiz_sync
//-------------------------------------------------------------------------
//IP : xilinx mmcm with "NO_BUFFER" input clock
class vc707clk_wiz_sync extends BlackBox {
val io = new Bundle {
val clk_in1 = Bool(INPUT)
val clk_out1 = Clock(OUTPUT)
val clk_out2 = Clock(OUTPUT)
val clk_out3 = Clock(OUTPUT)
val clk_out4 = Clock(OUTPUT)
val clk_out5 = Clock(OUTPUT)
val clk_out6 = Clock(OUTPUT)
val clk_out7 = Clock(OUTPUT)
val reset = Bool(INPUT)
val locked = Bool(OUTPUT)
}
}
//-------------------------------------------------------------------------
// vc707reset
//-------------------------------------------------------------------------
class vc707reset() extends BlackBox
{
val io = new Bundle{
val areset = Bool(INPUT)
val clock1 = Clock(INPUT)
val reset1 = Bool(OUTPUT)
val clock2 = Clock(INPUT)
val reset2 = Bool(OUTPUT)
val clock3 = Clock(INPUT)
val reset3 = Bool(OUTPUT)
val clock4 = Clock(INPUT)
val reset4 = Bool(OUTPUT)
}
}
//-------------------------------------------------------------------------
// sdio_spi_bridge
//-------------------------------------------------------------------------
class sdio_spi_bridge() extends BlackBox
{
val io = new Bundle{
val clk = Clock(INPUT)
val reset = Bool(INPUT)
val sd_cmd = Analog(1.W)
val sd_dat = Analog(4.W)
val spi_sck = Bool(INPUT)
val spi_cs = Bool(INPUT)
val spi_dq_o = Bits(INPUT,4)
val spi_dq_i = Bits(OUTPUT,4)
}
}

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src/main/scala/ip/xilinx/ibufds_gte2/ibufds_gte2.scala Normal file
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// See LICENSE for license details.
package sifive.fpgashells.ip.xilinx.ibufds_gte2
import Chisel._
//IP : xilinx unisim IBUFDS_GTE2
//Differential Signaling Input Buffer
//unparameterized
class IBUFDS_GTE2 extends BlackBox {
val io = new Bundle {
val O = Bool(OUTPUT)
val ODIV2 = Bool(OUTPUT)
val CEB = Bool(INPUT)
val I = Bool(INPUT)
val IB = Bool(INPUT)
}
}

401
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala Normal file
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// See LICENSE for license details.
package sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple}
// IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0
// Black Box
// Signals named _exactly_ as per Vivado generated verilog
// s : -{lock, cache, prot, qos}
trait VC707AXIToPCIeX1IOSerial extends Bundle {
//serial external pins
val pci_exp_txp = Bool(OUTPUT)
val pci_exp_txn = Bool(OUTPUT)
val pci_exp_rxp = Bool(INPUT)
val pci_exp_rxn = Bool(INPUT)
}
trait VC707AXIToPCIeX1IOClocksReset extends Bundle {
//clock, reset, control
val axi_aresetn = Bool(INPUT)
val axi_aclk_out = Clock(OUTPUT)
val axi_ctl_aclk_out = Clock(OUTPUT)
val mmcm_lock = Bool(OUTPUT)
}
//scalastyle:off
//turn off linter: blackbox name must match verilog module
class vc707axi_to_pcie_x1() extends BlackBox
{
val io = new Bundle with VC707AXIToPCIeX1IOSerial
with VC707AXIToPCIeX1IOClocksReset {
//refclk
val REFCLK = Bool(INPUT)
//clock, reset, control
val INTX_MSI_Request = Bool(INPUT)
val INTX_MSI_Grant = Bool(OUTPUT)
val MSI_enable = Bool(OUTPUT)
val MSI_Vector_Num = Bits(INPUT,5)
val MSI_Vector_Width = Bits(OUTPUT,3)
//interrupt
val interrupt_out = Bool(OUTPUT)
//axi slave
//-{lock, cache, prot, qos}
//slave interface write address
val s_axi_awid = Bits(INPUT,4)
val s_axi_awaddr = Bits(INPUT,32)
val s_axi_awregion = Bits(INPUT,4)
val s_axi_awlen = Bits(INPUT,8)
val s_axi_awsize = Bits(INPUT,3)
val s_axi_awburst = Bits(INPUT,2)
//val s_axi_awlock = Bool(INPUT)
//val s_axi_awcache = Bits(INPUT,4)
//val s_axi_awprot = Bits(INPUT,3)
//val s_axi_awqos = Bits(INPUT,4)
val s_axi_awvalid = Bool(INPUT)
val s_axi_awready = Bool(OUTPUT)
//slave interface write data
val s_axi_wdata = Bits(INPUT,64)
val s_axi_wstrb = Bits(INPUT,8)
val s_axi_wlast = Bool(INPUT)
val s_axi_wvalid = Bool(INPUT)
val s_axi_wready = Bool(OUTPUT)
//slave interface write response
val s_axi_bready = Bool(INPUT)
val s_axi_bid = Bits(OUTPUT,4)
val s_axi_bresp = Bits(OUTPUT,2)
val s_axi_bvalid = Bool(OUTPUT)
//slave interface read address
val s_axi_arid = Bits(INPUT,4)
val s_axi_araddr = Bits(INPUT,32)
val s_axi_arregion = Bits(INPUT,4)
val s_axi_arlen = Bits(INPUT,8)
val s_axi_arsize = Bits(INPUT,3)
val s_axi_arburst = Bits(INPUT,2)
//val s_axi_arlock = Bits(INPUT,1)
//val s_axi_arcache = Bits(INPUT,4)
//val s_axi_arprot = Bits(INPUT,3)
//val s_axi_arqos = Bits(INPUT,4)
val s_axi_arvalid = Bool(INPUT)
val s_axi_arready = Bool(OUTPUT)
//slave interface read data
val s_axi_rready = Bool(INPUT)
val s_axi_rid = Bits(OUTPUT,4)
val s_axi_rdata = Bits(OUTPUT,64)
val s_axi_rresp = Bits(OUTPUT,2)
val s_axi_rlast = Bool(OUTPUT)
val s_axi_rvalid = Bool(OUTPUT)
//axi master
//-{id,region,qos}
//slave interface write address ports
//val m_axi_awid = Bits(OUTPUT,4)
val m_axi_awaddr = Bits(OUTPUT,32)
//val m_axi_awregion = Bits(OUTPUT,4)
val m_axi_awlen = Bits(OUTPUT,8)
val m_axi_awsize = Bits(OUTPUT,3)
val m_axi_awburst = Bits(OUTPUT,2)
val m_axi_awlock = Bool(OUTPUT)
val m_axi_awcache = Bits(OUTPUT,4)
val m_axi_awprot = Bits(OUTPUT,3)
//val m_axi_awqos = Bits(OUTPUT,4)
val m_axi_awvalid = Bool(OUTPUT)
val m_axi_awready = Bool(INPUT)
//slave interface write data ports
val m_axi_wdata = Bits(OUTPUT,64)
val m_axi_wstrb = Bits(OUTPUT,8)
val m_axi_wlast = Bool(OUTPUT)
val m_axi_wvalid = Bool(OUTPUT)
val m_axi_wready = Bool(INPUT)
//slave interface write response ports
val m_axi_bready = Bool(OUTPUT)
//val m_axi_bid = Bits(INPUT,4)
val m_axi_bresp = Bits(INPUT,2)
val m_axi_bvalid = Bool(INPUT)
//slave interface read address ports
//val m_axi_arid = Bits(OUTPUT,4)
val m_axi_araddr = Bits(OUTPUT,32)
//val m_axi_arregion = Bits(OUTPUT,4)
val m_axi_arlen = Bits(OUTPUT,8)
val m_axi_arsize = Bits(OUTPUT,3)
val m_axi_arburst = Bits(OUTPUT,2)
val m_axi_arlock = Bits(OUTPUT,1)
val m_axi_arcache = Bits(OUTPUT,4)
val m_axi_arprot = Bits(OUTPUT,3)
//val m_axi_arqos = Bits(OUTPUT,4)
val m_axi_arvalid = Bool(OUTPUT)
val m_axi_arready = Bool(INPUT)
//slave interface read data ports
val m_axi_rready = Bool(OUTPUT)
//val m_axi_rid = Bits(INPUT,4)
val m_axi_rdata = Bits(INPUT,64)
val m_axi_rresp = Bits(INPUT,2)
val m_axi_rlast = Bool(INPUT)
val m_axi_rvalid = Bool(INPUT)
//axi lite slave for control
val s_axi_ctl_awaddr = Bits(INPUT,32)
val s_axi_ctl_awvalid = Bool(INPUT)
val s_axi_ctl_awready = Bool(OUTPUT)
val s_axi_ctl_wdata = Bits(INPUT,32)
val s_axi_ctl_wstrb = Bits(INPUT,4)
val s_axi_ctl_wvalid = Bool(INPUT)
val s_axi_ctl_wready = Bool(OUTPUT)
val s_axi_ctl_bresp = Bits(OUTPUT,2)
val s_axi_ctl_bvalid = Bool(OUTPUT)
val s_axi_ctl_bready = Bool(INPUT)
val s_axi_ctl_araddr = Bits(INPUT,32)
val s_axi_ctl_arvalid = Bool(INPUT)
val s_axi_ctl_arready = Bool(OUTPUT)
val s_axi_ctl_rdata = Bits(OUTPUT,32)
val s_axi_ctl_rresp = Bits(OUTPUT,2)
val s_axi_ctl_rvalid = Bool(OUTPUT)
val s_axi_ctl_rready = Bool(INPUT)
}
}
//scalastyle:off
//wrap vc707_axi_to_pcie_x1 black box in Nasti Bundles
class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
{
val device = new SimpleDevice("pci", Seq("xlnx,axi-pcie-host-1.00.a")) {
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val intc = "pcie_intc"
def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
def ofMap(x: Int) = Seq(0, 0, 0, x).flatMap(ofInt) ++ Seq(ResourceReference(intc)) ++ ofInt(x)
val extra = Map(
"#address-cells" -> ofInt(3),
"#size-cells" -> ofInt(2),
"#interrupt-cells" -> ofInt(1),
"device_type" -> Seq(ResourceString("pci")),
"interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
"interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap),
"ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, perms)) =>
ResourceMapping(address, BigInt(0x02000000) << 64, perms) },
"interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
"interrupt-controller" -> Nil,
"#address-cells" -> ofInt(0),
"#interrupt-cells" -> ofInt(1)))))
Description(name, mapping ++ extra)
}
}
val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x60000000L, 0x1fffffffL)),
resources = Seq(Resource(device, "ranges")),
executable = true,
supportsWrite = TransferSizes(1, 256),
supportsRead = TransferSizes(1, 256))),
beatBytes = 8)))
val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x50000000L, 0x03ffffffL)),
resources = device.reg("control"),
supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4),
interleavedId = Some(0))), // AXI4-Lite never interleaves responses
beatBytes = 4)))
val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters(
name = "VC707 PCIe",
id = IdRange(0, 1),
aligned = false)))))
val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
lazy val module = new LazyModuleImp(this) {
// The master on the control port must be AXI-lite
require (control.edgesIn(0).master.endId == 1)
// Must have exactly the right number of idBits
require (slave.edgesIn(0).bundle.idBits == 4)
class VC707AXIToPCIeX1IOBundle extends Bundle with VC707AXIToPCIeX1IOSerial
with VC707AXIToPCIeX1IOClocksReset;
val io = new Bundle {
val port = new VC707AXIToPCIeX1IOBundle
val slave_in = slave.bundleIn
val control_in = control.bundleIn
val master_out = master.bundleOut
val REFCLK = Bool(INPUT)
val interrupt_out = intnode.bundleOut
}
val blackbox = Module(new vc707axi_to_pcie_x1)
val s = io.slave_in(0)
val c = io.control_in(0)
val m = io.master_out(0)
//to top level
blackbox.io.axi_aresetn := io.port.axi_aresetn
io.port.axi_aclk_out := blackbox.io.axi_aclk_out
io.port.axi_ctl_aclk_out := blackbox.io.axi_ctl_aclk_out
io.port.mmcm_lock := blackbox.io.mmcm_lock
io.port.pci_exp_txp := blackbox.io.pci_exp_txp
io.port.pci_exp_txn := blackbox.io.pci_exp_txn
blackbox.io.pci_exp_rxp := io.port.pci_exp_rxp
blackbox.io.pci_exp_rxn := io.port.pci_exp_rxn
io.interrupt_out(0)(0) := blackbox.io.interrupt_out
blackbox.io.REFCLK := io.REFCLK
//s
//AXI4 signals ordered as per AXI4 Specification (Release D) Section A.2
//-{lock, cache, prot, qos}
//-{aclk, aresetn, awuser, wid, wuser, buser, ruser}
//global signals
//aclk :=
//aresetn :=
//slave interface write address
blackbox.io.s_axi_awid := s.aw.bits.id
blackbox.io.s_axi_awaddr := s.aw.bits.addr
blackbox.io.s_axi_awlen := s.aw.bits.len
blackbox.io.s_axi_awsize := s.aw.bits.size
blackbox.io.s_axi_awburst := s.aw.bits.burst
//blackbox.io.s_axi_awlock := s.aw.bits.lock
//blackbox.io.s_axi_awcache := s.aw.bits.cache
//blackbox.io.s_axi_awprot := s.aw.bits.prot
//blackbox.io.s_axi_awqos := s.aw.bits.qos
blackbox.io.s_axi_awregion := UInt(0)
//blackbox.io.awuser := s.aw.bits.user
blackbox.io.s_axi_awvalid := s.aw.valid
s.aw.ready := blackbox.io.s_axi_awready
//slave interface write data ports
//blackbox.io.s_axi_wid := s.w.bits.id
blackbox.io.s_axi_wdata := s.w.bits.data
blackbox.io.s_axi_wstrb := s.w.bits.strb
blackbox.io.s_axi_wlast := s.w.bits.last
//blackbox.io.s_axi_wuser := s.w.bits.user
blackbox.io.s_axi_wvalid := s.w.valid
s.w.ready := blackbox.io.s_axi_wready
//slave interface write response
s.b.bits.id := blackbox.io.s_axi_bid
s.b.bits.resp := blackbox.io.s_axi_bresp
//s.b.bits.user := blackbox.io.s_axi_buser
s.b.valid := blackbox.io.s_axi_bvalid
blackbox.io.s_axi_bready := s.b.ready
//slave AXI interface read address ports
blackbox.io.s_axi_arid := s.ar.bits.id
blackbox.io.s_axi_araddr := s.ar.bits.addr
blackbox.io.s_axi_arlen := s.ar.bits.len
blackbox.io.s_axi_arsize := s.ar.bits.size
blackbox.io.s_axi_arburst := s.ar.bits.burst
//blackbox.io.s_axi_arlock := s.ar.bits.lock
//blackbox.io.s_axi_arcache := s.ar.bits.cache
//blackbox.io.s_axi_arprot := s.ar.bits.prot
//blackbox.io.s_axi_arqos := s.ar.bits.qos
blackbox.io.s_axi_arregion := UInt(0)
//blackbox.io.s_axi_aruser := s.ar.bits.user
blackbox.io.s_axi_arvalid := s.ar.valid
s.ar.ready := blackbox.io.s_axi_arready
//slave AXI interface read data ports
s.r.bits.id := blackbox.io.s_axi_rid
s.r.bits.data := blackbox.io.s_axi_rdata
s.r.bits.resp := blackbox.io.s_axi_rresp
s.r.bits.last := blackbox.io.s_axi_rlast
//s.r.bits.ruser := blackbox.io.s_axi_ruser
s.r.valid := blackbox.io.s_axi_rvalid
blackbox.io.s_axi_rready := s.r.ready
//ctl
//axi-lite slave interface write address
blackbox.io.s_axi_ctl_awaddr := c.aw.bits.addr
blackbox.io.s_axi_ctl_awvalid := c.aw.valid
c.aw.ready := blackbox.io.s_axi_ctl_awready
//axi-lite slave interface write data ports
blackbox.io.s_axi_ctl_wdata := c.w.bits.data
blackbox.io.s_axi_ctl_wstrb := c.w.bits.strb
blackbox.io.s_axi_ctl_wvalid := c.w.valid
c.w.ready := blackbox.io.s_axi_ctl_wready
//axi-lite slave interface write response
blackbox.io.s_axi_ctl_bready := c.b.ready
c.b.bits.id := UInt(0)
c.b.bits.resp := blackbox.io.s_axi_ctl_bresp
c.b.valid := blackbox.io.s_axi_ctl_bvalid
//axi-lite slave AXI interface read address ports
blackbox.io.s_axi_ctl_araddr := c.ar.bits.addr
blackbox.io.s_axi_ctl_arvalid := c.ar.valid
c.ar.ready := blackbox.io.s_axi_ctl_arready
//slave AXI interface read data ports
blackbox.io.s_axi_ctl_rready := c.r.ready
c.r.bits.id := UInt(0)
c.r.bits.data := blackbox.io.s_axi_ctl_rdata
c.r.bits.resp := blackbox.io.s_axi_ctl_rresp
c.r.bits.last := Bool(true)
c.r.valid := blackbox.io.s_axi_ctl_rvalid
//m
//AXI4 signals ordered per AXI4 Specification (Release D) Section A.2
//-{id,region,qos}
//-{aclk, aresetn, awuser, wid, wuser, buser, ruser}
//global signals
//aclk :=
//aresetn :=
//master interface write address
m.aw.bits.id := UInt(0)
m.aw.bits.addr := blackbox.io.m_axi_awaddr
m.aw.bits.len := blackbox.io.m_axi_awlen
m.aw.bits.size := blackbox.io.m_axi_awsize
m.aw.bits.burst := blackbox.io.m_axi_awburst
m.aw.bits.lock := blackbox.io.m_axi_awlock
m.aw.bits.cache := blackbox.io.m_axi_awcache
m.aw.bits.prot := blackbox.io.m_axi_awprot
m.aw.bits.qos := UInt(0)
//m.aw.bits.region := blackbox.io.m_axi_awregion
//m.aw.bits.user := blackbox.io.m_axi_awuser
m.aw.valid := blackbox.io.m_axi_awvalid
blackbox.io.m_axi_awready := m.aw.ready
//master interface write data ports
m.w.bits.data := blackbox.io.m_axi_wdata
m.w.bits.strb := blackbox.io.m_axi_wstrb
m.w.bits.last := blackbox.io.m_axi_wlast
//m.w.bits.user := blackbox.io.m_axi_wuser
m.w.valid := blackbox.io.m_axi_wvalid
blackbox.io.m_axi_wready := m.w.ready
//master interface write response
//blackbox.io.m_axi_bid := m.b.bits.id
blackbox.io.m_axi_bresp := m.b.bits.resp
//blackbox.io.m_axi_buser := m.b.bits.user
blackbox.io.m_axi_bvalid := m.b.valid
m.b.ready := blackbox.io.m_axi_bready
//master AXI interface read address ports
m.ar.bits.id := UInt(0)
m.ar.bits.addr := blackbox.io.m_axi_araddr
m.ar.bits.len := blackbox.io.m_axi_arlen
m.ar.bits.size := blackbox.io.m_axi_arsize
m.ar.bits.burst := blackbox.io.m_axi_arburst
m.ar.bits.lock := blackbox.io.m_axi_arlock
m.ar.bits.cache := blackbox.io.m_axi_arcache
m.ar.bits.prot := blackbox.io.m_axi_arprot
m.ar.bits.qos := UInt(0)
//m.ar.bits.region := blackbox.io.m_axi_arregion
//m.ar.bits.user := blackbox.io.s_axi_aruser
m.ar.valid := blackbox.io.m_axi_arvalid
blackbox.io.m_axi_arready := m.ar.ready
//master AXI interface read data ports
//blackbox.io.m_axi_rid := m.r.bits.id
blackbox.io.m_axi_rdata := m.r.bits.data
blackbox.io.m_axi_rresp := m.r.bits.resp
blackbox.io.m_axi_rlast := m.r.bits.last
//blackbox.io.s_axi_ruser := s.bits.ruser
blackbox.io.m_axi_rvalid := m.r.valid
m.r.ready := blackbox.io.m_axi_rready
}
}

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src/main/scala/ip/xilinx/vc707mig/vc707mig.scala Normal file
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// See LICENSE for license details.
package sifive.fpgashells.ip.xilinx.vc707mig
import Chisel._
import chisel3.experimental.{Analog,attach}
import freechips.rocketchip.config._
// IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
// Black Box
trait VC707MIGIODDR extends Bundle {
val ddr3_addr = Bits(OUTPUT,14)
val ddr3_ba = Bits(OUTPUT,3)
val ddr3_ras_n = Bool(OUTPUT)
val ddr3_cas_n = Bool(OUTPUT)
val ddr3_we_n = Bool(OUTPUT)
val ddr3_reset_n = Bool(OUTPUT)
val ddr3_ck_p = Bits(OUTPUT,1)
val ddr3_ck_n = Bits(OUTPUT,1)
val ddr3_cke = Bits(OUTPUT,1)
val ddr3_cs_n = Bits(OUTPUT,1)
val ddr3_dm = Bits(OUTPUT,8)
val ddr3_odt = Bits(OUTPUT,1)
val ddr3_dq = Analog(64.W)
val ddr3_dqs_n = Analog(8.W)
val ddr3_dqs_p = Analog(8.W)
}
//reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
trait VC707MIGIOClocksReset extends Bundle {
//inputs
//"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
val sys_clk_i = Bool(INPUT)
//user interface signals
val ui_clk = Clock(OUTPUT)
val ui_clk_sync_rst = Bool(OUTPUT)
val mmcm_locked = Bool(OUTPUT)
val aresetn = Bool(INPUT)
//misc
val init_calib_complete = Bool(OUTPUT)
val sys_rst = Bool(INPUT)
}
//scalastyle:off
//turn off linter: blackbox name must match verilog module
class vc707mig(implicit val p:Parameters) extends BlackBox
{
val io = new Bundle with VC707MIGIODDR
with VC707MIGIOClocksReset {
// User interface signals
val app_sr_req = Bool(INPUT)
val app_ref_req = Bool(INPUT)
val app_zq_req = Bool(INPUT)
val app_sr_active = Bool(OUTPUT)
val app_ref_ack = Bool(OUTPUT)
val app_zq_ack = Bool(OUTPUT)
//axi_s
//slave interface write address ports
val s_axi_awid = Bits(INPUT,4)
val s_axi_awaddr = Bits(INPUT,30)
val s_axi_awlen = Bits(INPUT,8)
val s_axi_awsize = Bits(INPUT,3)
val s_axi_awburst = Bits(INPUT,2)
val s_axi_awlock = Bits(INPUT,1)
val s_axi_awcache = Bits(INPUT,4)
val s_axi_awprot = Bits(INPUT,3)
val s_axi_awqos = Bits(INPUT,4)
val s_axi_awvalid = Bool(INPUT)
val s_axi_awready = Bool(OUTPUT)
//slave interface write data ports
val s_axi_wdata = Bits(INPUT,64)
val s_axi_wstrb = Bits(INPUT,8)
val s_axi_wlast = Bool(INPUT)
val s_axi_wvalid = Bool(INPUT)
val s_axi_wready = Bool(OUTPUT)
//slave interface write response ports
val s_axi_bready = Bool(INPUT)
val s_axi_bid = Bits(OUTPUT,4)
val s_axi_bresp = Bits(OUTPUT,2)
val s_axi_bvalid = Bool(OUTPUT)
//slave interface read address ports
val s_axi_arid = Bits(INPUT,4)
val s_axi_araddr = Bits(INPUT,30)
val s_axi_arlen = Bits(INPUT,8)
val s_axi_arsize = Bits(INPUT,3)
val s_axi_arburst = Bits(INPUT,2)
val s_axi_arlock = Bits(INPUT,1)
val s_axi_arcache = Bits(INPUT,4)
val s_axi_arprot = Bits(INPUT,3)
val s_axi_arqos = Bits(INPUT,4)
val s_axi_arvalid = Bool(INPUT)
val s_axi_arready = Bool(OUTPUT)
//slave interface read data ports
val s_axi_rready = Bool(INPUT)
val s_axi_rid = Bits(OUTPUT,4)
val s_axi_rdata = Bits(OUTPUT,64)
val s_axi_rresp = Bits(OUTPUT,2)
val s_axi_rlast = Bool(OUTPUT)
val s_axi_rvalid = Bool(OUTPUT)
//misc
val device_temp = Bits(OUTPUT,12)
}
}
//scalastyle:on

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src/main/scala/shell/xilinx/ArtyShell.scala Normal file
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// See LICENSE for license details.
package sifive.fpgashells.shell.xilinx.artyshell
import Chisel._
import chisel3.core.{Input, Output, attach}
import chisel3.experimental.{RawModule, Analog, withClockAndReset}
import freechips.rocketchip.config._
import freechips.rocketchip.devices.debug._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.pwm._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.pinctrl.{BasePin}
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, mmcm, reset_sys, PowerOnResetFPGAOnly}
//-------------------------------------------------------------------------
// ArtyShell
//-------------------------------------------------------------------------
abstract class ArtyShell(implicit val p: Parameters) extends RawModule {
//-----------------------------------------------------------------------
// Interface
//-----------------------------------------------------------------------
// Clock & Reset
val CLK100MHZ = IO(Input(Clock()))
val ck_rst = IO(Input(Bool()))
// Green LEDs
val led_0 = IO(Analog(1.W))
val led_1 = IO(Analog(1.W))
val led_2 = IO(Analog(1.W))
val led_3 = IO(Analog(1.W))
// RGB LEDs, 3 pins each
val led0_r = IO(Analog(1.W))
val led0_g = IO(Analog(1.W))
val led0_b = IO(Analog(1.W))
val led1_r = IO(Analog(1.W))
val led1_g = IO(Analog(1.W))
val led1_b = IO(Analog(1.W))
val led2_r = IO(Analog(1.W))
val led2_g = IO(Analog(1.W))
val led2_b = IO(Analog(1.W))
// Sliding switches
val sw_0 = IO(Analog(1.W))
val sw_1 = IO(Analog(1.W))
val sw_2 = IO(Analog(1.W))
val sw_3 = IO(Analog(1.W))
// Buttons. First 3 used as GPIO, the last is used as wakeup
val btn_0 = IO(Analog(1.W))
val btn_1 = IO(Analog(1.W))
val btn_2 = IO(Analog(1.W))
val btn_3 = IO(Analog(1.W))
// Dedicated QSPI interface
val qspi_cs = IO(Analog(1.W))
val qspi_sck = IO(Analog(1.W))
val qspi_dq = IO(Vec(4, Analog(1.W)))
// UART0
val uart_rxd_out = IO(Analog(1.W))
val uart_txd_in = IO(Analog(1.W))
// JA (Used for more generic GPIOs)
val ja_0 = IO(Analog(1.W))
val ja_1 = IO(Analog(1.W))
val ja_2 = IO(Analog(1.W))
val ja_3 = IO(Analog(1.W))
val ja_4 = IO(Analog(1.W))
val ja_5 = IO(Analog(1.W))
val ja_6 = IO(Analog(1.W))
val ja_7 = IO(Analog(1.W))
// JD (used for JTAG connection)
val jd_0 = IO(Analog(1.W)) // TDO
val jd_1 = IO(Analog(1.W)) // TRST_n
val jd_2 = IO(Analog(1.W)) // TCK
val jd_4 = IO(Analog(1.W)) // TDI
val jd_5 = IO(Analog(1.W)) // TMS
val jd_6 = IO(Analog(1.W)) // SRST_n
// ChipKit Digital I/O Pins
val ck_io = IO(Vec(20, Analog(1.W)))
// ChipKit SPI
val ck_miso = IO(Analog(1.W))
val ck_mosi = IO(Analog(1.W))
val ck_ss = IO(Analog(1.W))
val ck_sck = IO(Analog(1.W))
//-----------------------------------------------------------------------
// Wire declrations
//-----------------------------------------------------------------------
// Note: these frequencies are approximate.
val clock_8MHz = Wire(Clock())
val clock_32MHz = Wire(Clock())
val clock_65MHz = Wire(Clock())
val mmcm_locked = Wire(Bool())
val reset_core = Wire(Bool())
val reset_bus = Wire(Bool())
val reset_periph = Wire(Bool())
val reset_intcon_n = Wire(Bool())
val reset_periph_n = Wire(Bool())
val SRST_n = Wire(Bool())
val dut_jtag_TCK = Wire(Clock())
val dut_jtag_TMS = Wire(Bool())
val dut_jtag_TDI = Wire(Bool())
val dut_jtag_TDO = Wire(Bool())
val dut_jtag_reset = Wire(Bool())
val dut_ndreset = Wire(Bool())
//-----------------------------------------------------------------------
// Clock Generator
//-----------------------------------------------------------------------
// Mixed-mode clock generator
val ip_mmcm = Module(new mmcm())
ip_mmcm.io.clk_in1 := CLK100MHZ
clock_8MHz := ip_mmcm.io.clk_out1 // 8.388 MHz = 32.768 kHz * 256
clock_65MHz := ip_mmcm.io.clk_out2 // 65 Mhz
clock_32MHz := ip_mmcm.io.clk_out3 // 65/2 Mhz
ip_mmcm.io.resetn := ck_rst
mmcm_locked := ip_mmcm.io.locked
//-----------------------------------------------------------------------
// System Reset
//-----------------------------------------------------------------------
// processor system reset module
val ip_reset_sys = Module(new reset_sys())
ip_reset_sys.io.slowest_sync_clk := clock_8MHz
ip_reset_sys.io.ext_reset_in := ck_rst & SRST_n
ip_reset_sys.io.aux_reset_in := true.B
ip_reset_sys.io.mb_debug_sys_rst := dut_ndreset
ip_reset_sys.io.dcm_locked := mmcm_locked
reset_core := ip_reset_sys.io.mb_reset
reset_bus := ip_reset_sys.io.bus_struct_reset
reset_periph := ip_reset_sys.io.peripheral_reset
reset_intcon_n := ip_reset_sys.io.interconnect_aresetn
reset_periph_n := ip_reset_sys.io.peripheral_aresetn
//-----------------------------------------------------------------------
// SPI Flash
//-----------------------------------------------------------------------
def connectSPIFlash(dut: HasPeripherySPIFlashModuleImp): Unit = {
val qspiParams = p(PeripherySPIFlashKey)
if (!qspiParams.isEmpty) {
val qspi_params = qspiParams(0)
val qspi_pins = Wire(new SPIPins(() => {new BasePin()}, qspi_params))
qspi_pins.fromPort(
dut.qspi(0),
dut.clock,
dut.reset,
syncStages = qspi_params.sampleDelay
)
IOBUF(qspi_sck, dut.qspi(0).sck)
IOBUF(qspi_cs, dut.qspi(0).cs(0))
(qspi_dq zip qspi_pins.dq).foreach {
case(a, b) => IOBUF(a,b)
}
}
}
//---------------------------------------------------------------------
// Debug JTAG
//---------------------------------------------------------------------
def connectDebugJTAG(dut: HasPeripheryDebugModuleImp): SystemJTAGIO = {
//-------------------------------------------------------------------
// JTAG Reset
//-------------------------------------------------------------------
val jtag_power_on_reset = PowerOnResetFPGAOnly(clock_32MHz)
dut_jtag_reset := jtag_power_on_reset
//-------------------------------------------------------------------
// JTAG IOBUFs
//-------------------------------------------------------------------
dut_jtag_TCK := IBUFG(IOBUF(jd_2).asClock)
dut_jtag_TMS := IOBUF(jd_5)
PULLUP(jd_5)
dut_jtag_TDI := IOBUF(jd_4)
PULLUP(jd_4)
IOBUF(jd_0, dut_jtag_TDO)
SRST_n := IOBUF(jd_6)
PULLUP(jd_6)
//-------------------------------------------------------------------
// JTAG PINS
//-------------------------------------------------------------------
val djtag = dut.debug.systemjtag.get
djtag.jtag.TCK := dut_jtag_TCK
djtag.jtag.TMS := dut_jtag_TMS
djtag.jtag.TDI := dut_jtag_TDI
dut_jtag_TDO := djtag.jtag.TDO.data
djtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
djtag.reset := dut_jtag_reset
dut_ndreset := dut.debug.ndreset
djtag
}
//---------------------------------------------------------------------
// UART
//---------------------------------------------------------------------
def connectUART(dut: HasPeripheryUARTModuleImp): Unit = {
val uartParams = p(PeripheryUARTKey)
if (!uartParams.isEmpty) {
IOBUF(uart_rxd_out, dut.uart(0).txd)
dut.uart(0).rxd := IOBUF(uart_txd_in)
}
}
}

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src/main/scala/shell/xilinx/VC707Shell.scala Normal file
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// See LICENSE for license details.
package sifive.fpgashells.shell.xilinx.vc707shell
import Chisel._
import chisel3.core.{Input, Output, attach}
import chisel3.experimental.{RawModule, Analog, withClockAndReset}
import freechips.rocketchip.config._
import freechips.rocketchip.devices.debug._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
import sifive.fpgashells.ip.xilinx.{IBUFDS, PowerOnResetFPGAOnly, sdio_spi_bridge, vc707clk_wiz_sync, vc707reset}
//-------------------------------------------------------------------------
// VC707Shell
//-------------------------------------------------------------------------
abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
//-----------------------------------------------------------------------
// Interface
//-----------------------------------------------------------------------
// 200Mhz differential sysclk
val sys_diff_clock_clk_n = IO(Input(Bool()))
val sys_diff_clock_clk_p = IO(Input(Bool()))
// active high reset
val reset = IO(Input(Bool()))
// DDR SDRAM
val ddr3_addr = IO(Output(UInt(14.W)))
val ddr3_ba = IO(Output(UInt(3.W)))
val ddr3_cas_n = IO(Output(Bool()))
val ddr3_ck_p = IO(Output(Bool()))
val ddr3_ck_n = IO(Output(Bool()))
val ddr3_cke = IO(Output(Bool()))
val ddr3_cs_n = IO(Output(Bool()))
val ddr3_dm = IO(Output(UInt(8.W)))
val ddr3_dq = IO(Analog(64.W))
val ddr3_dqs_n = IO(Analog(8.W))
val ddr3_dqs_p = IO(Analog(8.W))
val ddr3_odt = IO(Output(Bool()))
val ddr3_ras_n = IO(Output(Bool()))
val ddr3_reset_n = IO(Output(Bool()))
val ddr3_we_n = IO(Output(Bool()))
// LED
val led = IO(Vec(8, Output(Bool())))
// UART
val uart_tx = IO(Output(Bool()))
val uart_rx = IO(Input(Bool()))
val uart_rtsn = IO(Output(Bool()))
val uart_ctsn = IO(Input(Bool()))
// SDIO
val sdio_clk = IO(Output(Bool()))
val sdio_cmd = IO(Analog(1.W))
val sdio_dat = IO(Analog(4.W))
// JTAG
val jtag_TCK = IO(Input(Clock()))
val jtag_TMS = IO(Input(Bool()))
val jtag_TDI = IO(Input(Bool()))
val jtag_TDO = IO(Output(Bool()))
// PCIe
val pci_exp_txp = IO(Output(Bool()))
val pci_exp_txn = IO(Output(Bool()))
val pci_exp_rxp = IO(Input(Bool()))
val pci_exp_rxn = IO(Input(Bool()))
val pci_exp_refclk_rxp = IO(Input(Bool()))
val pci_exp_refclk_rxn = IO(Input(Bool()))
//-----------------------------------------------------------------------
// Wire declrations
//-----------------------------------------------------------------------
val sys_clock = Wire(Clock())
val sys_reset = Wire(Bool())
val dut_clock = Wire(Clock())
val dut_reset = Wire(Bool())
val dut_resetn = Wire(Bool())
val dut_ndreset = Wire(Bool())
val sd_spi_sck = Wire(Bool())
val sd_spi_cs = Wire(Bool())
val sd_spi_dq_i = Wire(Vec(4, Bool()))
val sd_spi_dq_o = Wire(Vec(4, Bool()))
val do_reset = Wire(Bool())
val mig_mmcm_locked = Wire(Bool())
val mig_sys_reset = Wire(Bool())
val mig_clock = Wire(Clock())
val mig_reset = Wire(Bool())
val mig_resetn = Wire(Bool())
val pcie_dat_reset = Wire(Bool())
val pcie_dat_resetn = Wire(Bool())
val pcie_cfg_reset = Wire(Bool())
val pcie_cfg_resetn = Wire(Bool())
val pcie_dat_clock = Wire(Clock())
val pcie_cfg_clock = Wire(Clock())
val mmcm_lock_pcie = Wire(Bool())
//-----------------------------------------------------------------------
// Differential clock
//-----------------------------------------------------------------------
val sys_clk_ibufds = Module(new IBUFDS)
sys_clk_ibufds.io.I := sys_diff_clock_clk_p
sys_clk_ibufds.io.IB := sys_diff_clock_clk_n
//-----------------------------------------------------------------------
// System clock and reset
//-----------------------------------------------------------------------
// Clock that drives the clock generator and the MIG
sys_clock := sys_clk_ibufds.io.O.asClock
// Allow the debug module to reset everything. Resets the MIG
sys_reset := reset | dut_ndreset
//-----------------------------------------------------------------------
// Clock Generator
//-----------------------------------------------------------------------
val coreplex_mmcm = Module(new vc707clk_wiz_sync)
coreplex_mmcm.io.clk_in1 := sys_clock.asUInt
coreplex_mmcm.io.reset := mig_sys_reset
val clk12_5 = coreplex_mmcm.io.clk_out1
val clk25 = coreplex_mmcm.io.clk_out2
val clk37_5 = coreplex_mmcm.io.clk_out3
val clk50 = coreplex_mmcm.io.clk_out4
val clk100 = coreplex_mmcm.io.clk_out5
val clk150 = coreplex_mmcm.io.clk_out6
val clk75 = coreplex_mmcm.io.clk_out7
val coreplex_mmcm_locked = coreplex_mmcm.io.locked
// DUT clock
dut_clock := clk37_5
//-----------------------------------------------------------------------
// System reset
//-----------------------------------------------------------------------
do_reset := !mig_mmcm_locked || !mmcm_lock_pcie || mig_sys_reset || !coreplex_mmcm_locked
mig_resetn := !mig_reset
dut_resetn := !dut_reset
pcie_dat_resetn := !pcie_dat_reset
pcie_cfg_resetn := !pcie_cfg_reset
val safe_reset = Module(new vc707reset)
safe_reset.io.areset := do_reset
safe_reset.io.clock1 := mig_clock
mig_reset := safe_reset.io.reset1
safe_reset.io.clock2 := pcie_dat_clock
pcie_dat_reset := safe_reset.io.reset2
safe_reset.io.clock3 := pcie_cfg_clock
pcie_cfg_reset := safe_reset.io.reset3
safe_reset.io.clock4 := dut_clock
dut_reset := safe_reset.io.reset4
//---------------------------------------------------------------------
// Debug JTAG
//---------------------------------------------------------------------
def connectDebugJTAG(dut: HasPeripheryDebugModuleImp): Unit = {
val djtag = dut.debug.systemjtag.get
djtag.jtag.TCK := jtag_TCK
djtag.jtag.TMS := jtag_TMS
djtag.jtag.TDI := jtag_TDI
jtag_TDO := djtag.jtag.TDO.data
djtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
djtag.reset := PowerOnResetFPGAOnly(dut_clock)
dut_ndreset := dut.debug.ndreset
}
//-----------------------------------------------------------------------
// UART
//-----------------------------------------------------------------------
uart_rtsn := false.B
def connectUART(dut: HasPeripheryUARTModuleImp): Unit = {
val uartParams = p(PeripheryUARTKey)
if (!uartParams.isEmpty) {
// synchronize uart_rx
val uart_rx_sync_reg0 = RegInit(true.B)
uart_rx_sync_reg0 := uart_rx
val uart_rx_sync_reg1 = RegInit(true.B)
uart_rx_sync_reg1 := uart_rx_sync_reg0
// uart connections
dut.uart(0).rxd := uart_rx_sync_reg1
uart_tx := dut.uart(0).txd
}
}
//-----------------------------------------------------------------------
// SPI
//-----------------------------------------------------------------------
def connectSPI(dut: HasPeripherySPIModuleImp): Unit = {
// SPI
sd_spi_sck := dut.spi(0).sck
sd_spi_cs := dut.spi(0).cs(0)
dut.spi(0).dq.zipWithIndex.foreach {
case(pin, idx) =>
sd_spi_dq_o(idx) := pin.o
pin.i := sd_spi_dq_i(idx)
}
//-------------------------------------------------------------------
// SDIO <> SPI Bridge
//-------------------------------------------------------------------
val ip_sdio_spi = Module(new sdio_spi_bridge())
ip_sdio_spi.io.clk := dut_clock
ip_sdio_spi.io.reset := dut_reset
// SDIO
attach(sdio_dat, ip_sdio_spi.io.sd_dat)
attach(sdio_cmd, ip_sdio_spi.io.sd_cmd)
sdio_clk := ip_sdio_spi.io.spi_sck
// SPI
ip_sdio_spi.io.spi_sck := sd_spi_sck
ip_sdio_spi.io.spi_cs := sd_spi_cs
sd_spi_dq_i := ip_sdio_spi.io.spi_dq_i.toBools
ip_sdio_spi.io.spi_dq_o := sd_spi_dq_o.asUInt
}
//---------------------------------------------------------------------
// MIG
//---------------------------------------------------------------------
def connectMIG(dut: HasMemoryXilinxVC707MIGModuleImp): Unit = {
// Clock & Reset
dut.xilinxvc707mig.sys_clk_i := sys_clock.asUInt
mig_clock := dut.xilinxvc707mig.ui_clk
mig_sys_reset := dut.xilinxvc707mig.ui_clk_sync_rst
mig_mmcm_locked := dut.xilinxvc707mig.mmcm_locked
dut.xilinxvc707mig.aresetn := mig_resetn
dut.xilinxvc707mig.sys_rst := sys_reset
// Outputs
ddr3_addr := dut.xilinxvc707mig.ddr3_addr
ddr3_ba := dut.xilinxvc707mig.ddr3_ba
ddr3_ras_n := dut.xilinxvc707mig.ddr3_ras_n
ddr3_cas_n := dut.xilinxvc707mig.ddr3_cas_n
ddr3_we_n := dut.xilinxvc707mig.ddr3_we_n
ddr3_reset_n := dut.xilinxvc707mig.ddr3_reset_n
ddr3_ck_p := dut.xilinxvc707mig.ddr3_ck_p
ddr3_ck_n := dut.xilinxvc707mig.ddr3_ck_n
ddr3_cke := dut.xilinxvc707mig.ddr3_cke
ddr3_cs_n := dut.xilinxvc707mig.ddr3_cs_n
ddr3_dm := dut.xilinxvc707mig.ddr3_dm
ddr3_odt := dut.xilinxvc707mig.ddr3_odt
attach(ddr3_dq, dut.xilinxvc707mig.ddr3_dq)
attach(ddr3_dqs_n, dut.xilinxvc707mig.ddr3_dqs_n)
attach(ddr3_dqs_p, dut.xilinxvc707mig.ddr3_dqs_p)
}
//---------------------------------------------------------------------
// PCIE
//---------------------------------------------------------------------
def connectPCIe(dut: HasSystemXilinxVC707PCIeX1ModuleImp): Unit = {
// Clock & Reset
dut.xilinxvc707pcie.axi_aresetn := pcie_dat_resetn
pcie_dat_clock := dut.xilinxvc707pcie.axi_aclk_out
pcie_cfg_clock := dut.xilinxvc707pcie.axi_ctl_aclk_out
mmcm_lock_pcie := dut.xilinxvc707pcie.mmcm_lock
dut.xilinxvc707pcie.axi_ctl_aresetn := pcie_dat_resetn
dut.xilinxvc707pcie.REFCLK_rxp := pci_exp_refclk_rxp
dut.xilinxvc707pcie.REFCLK_rxn := pci_exp_refclk_rxn
// PCIeX1 connections
pci_exp_txp := dut.xilinxvc707pcie.pci_exp_txp
pci_exp_txn := dut.xilinxvc707pcie.pci_exp_txn
dut.xilinxvc707pcie.pci_exp_rxp := pci_exp_rxp
dut.xilinxvc707pcie.pci_exp_rxn := pci_exp_rxn
}
}