307 lines
11 KiB
Scala
307 lines
11 KiB
Scala
// See LICENSE for license details.
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package sifive.fpgashells.shell.xilinx.vc707shell
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import Chisel._
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import chisel3.core.{Input, Output, attach}
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import chisel3.experimental.{RawModule, Analog, withClockAndReset}
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import freechips.rocketchip.config._
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import freechips.rocketchip.devices.debug._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
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import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
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import sifive.fpgashells.ip.xilinx.{IBUFDS, PowerOnResetFPGAOnly, sdio_spi_bridge, vc707clk_wiz_sync, vc707reset}
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//-------------------------------------------------------------------------
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// VC707Shell
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//-------------------------------------------------------------------------
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abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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//-----------------------------------------------------------------------
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// Interface
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//-----------------------------------------------------------------------
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// 200Mhz differential sysclk
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val sys_diff_clock_clk_n = IO(Input(Bool()))
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val sys_diff_clock_clk_p = IO(Input(Bool()))
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// active high reset
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val reset = IO(Input(Bool()))
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// DDR SDRAM
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val ddr3_addr = IO(Output(UInt(14.W)))
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val ddr3_ba = IO(Output(UInt(3.W)))
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val ddr3_cas_n = IO(Output(Bool()))
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val ddr3_ck_p = IO(Output(Bool()))
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val ddr3_ck_n = IO(Output(Bool()))
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val ddr3_cke = IO(Output(Bool()))
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val ddr3_cs_n = IO(Output(Bool()))
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val ddr3_dm = IO(Output(UInt(8.W)))
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val ddr3_dq = IO(Analog(64.W))
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val ddr3_dqs_n = IO(Analog(8.W))
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val ddr3_dqs_p = IO(Analog(8.W))
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val ddr3_odt = IO(Output(Bool()))
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val ddr3_ras_n = IO(Output(Bool()))
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val ddr3_reset_n = IO(Output(Bool()))
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val ddr3_we_n = IO(Output(Bool()))
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// LED
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val led = IO(Vec(8, Output(Bool())))
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// UART
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val uart_tx = IO(Output(Bool()))
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val uart_rx = IO(Input(Bool()))
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val uart_rtsn = IO(Output(Bool()))
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val uart_ctsn = IO(Input(Bool()))
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// SDIO
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val sdio_clk = IO(Output(Bool()))
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val sdio_cmd = IO(Analog(1.W))
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val sdio_dat = IO(Analog(4.W))
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// JTAG
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val jtag_TCK = IO(Input(Clock()))
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val jtag_TMS = IO(Input(Bool()))
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val jtag_TDI = IO(Input(Bool()))
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val jtag_TDO = IO(Output(Bool()))
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// PCIe
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val pci_exp_txp = IO(Output(Bool()))
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val pci_exp_txn = IO(Output(Bool()))
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val pci_exp_rxp = IO(Input(Bool()))
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val pci_exp_rxn = IO(Input(Bool()))
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val pci_exp_refclk_rxp = IO(Input(Bool()))
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val pci_exp_refclk_rxn = IO(Input(Bool()))
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//-----------------------------------------------------------------------
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// Wire declrations
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//-----------------------------------------------------------------------
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val sys_clock = Wire(Clock())
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val sys_reset = Wire(Bool())
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val dut_clock = Wire(Clock())
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val dut_reset = Wire(Bool())
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val dut_resetn = Wire(Bool())
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val dut_ndreset = Wire(Bool())
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val sd_spi_sck = Wire(Bool())
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val sd_spi_cs = Wire(Bool())
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val sd_spi_dq_i = Wire(Vec(4, Bool()))
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val sd_spi_dq_o = Wire(Vec(4, Bool()))
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val do_reset = Wire(Bool())
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val mig_mmcm_locked = Wire(Bool())
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val mig_sys_reset = Wire(Bool())
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val mig_clock = Wire(Clock())
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val mig_reset = Wire(Bool())
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val mig_resetn = Wire(Bool())
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val pcie_dat_reset = Wire(Bool())
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val pcie_dat_resetn = Wire(Bool())
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val pcie_cfg_reset = Wire(Bool())
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val pcie_cfg_resetn = Wire(Bool())
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val pcie_dat_clock = Wire(Clock())
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val pcie_cfg_clock = Wire(Clock())
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val mmcm_lock_pcie = Wire(Bool())
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//-----------------------------------------------------------------------
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// Differential clock
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//-----------------------------------------------------------------------
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val sys_clk_ibufds = Module(new IBUFDS)
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sys_clk_ibufds.io.I := sys_diff_clock_clk_p
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sys_clk_ibufds.io.IB := sys_diff_clock_clk_n
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//-----------------------------------------------------------------------
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// System clock and reset
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//-----------------------------------------------------------------------
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// Clock that drives the clock generator and the MIG
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sys_clock := sys_clk_ibufds.io.O.asClock
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// Allow the debug module to reset everything. Resets the MIG
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sys_reset := reset | dut_ndreset
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//-----------------------------------------------------------------------
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// Clock Generator
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//-----------------------------------------------------------------------
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val coreplex_mmcm = Module(new vc707clk_wiz_sync)
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coreplex_mmcm.io.clk_in1 := sys_clock.asUInt
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coreplex_mmcm.io.reset := mig_sys_reset
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val clk12_5 = coreplex_mmcm.io.clk_out1
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val clk25 = coreplex_mmcm.io.clk_out2
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val clk37_5 = coreplex_mmcm.io.clk_out3
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val clk50 = coreplex_mmcm.io.clk_out4
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val clk100 = coreplex_mmcm.io.clk_out5
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val clk150 = coreplex_mmcm.io.clk_out6
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val clk75 = coreplex_mmcm.io.clk_out7
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val coreplex_mmcm_locked = coreplex_mmcm.io.locked
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// DUT clock
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dut_clock := clk37_5
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//-----------------------------------------------------------------------
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// System reset
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//-----------------------------------------------------------------------
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do_reset := !mig_mmcm_locked || !mmcm_lock_pcie || mig_sys_reset || !coreplex_mmcm_locked
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mig_resetn := !mig_reset
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dut_resetn := !dut_reset
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pcie_dat_resetn := !pcie_dat_reset
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pcie_cfg_resetn := !pcie_cfg_reset
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val safe_reset = Module(new vc707reset)
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safe_reset.io.areset := do_reset
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safe_reset.io.clock1 := mig_clock
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mig_reset := safe_reset.io.reset1
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safe_reset.io.clock2 := pcie_dat_clock
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pcie_dat_reset := safe_reset.io.reset2
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safe_reset.io.clock3 := pcie_cfg_clock
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pcie_cfg_reset := safe_reset.io.reset3
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safe_reset.io.clock4 := dut_clock
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dut_reset := safe_reset.io.reset4
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//---------------------------------------------------------------------
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// Debug JTAG
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//---------------------------------------------------------------------
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def connectDebugJTAG(dut: HasPeripheryDebugModuleImp): Unit = {
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val djtag = dut.debug.systemjtag.get
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djtag.jtag.TCK := jtag_TCK
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djtag.jtag.TMS := jtag_TMS
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djtag.jtag.TDI := jtag_TDI
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jtag_TDO := djtag.jtag.TDO.data
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djtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
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djtag.reset := PowerOnResetFPGAOnly(dut_clock)
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dut_ndreset := dut.debug.ndreset
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}
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//-----------------------------------------------------------------------
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// UART
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//-----------------------------------------------------------------------
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uart_rtsn := false.B
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def connectUART(dut: HasPeripheryUARTModuleImp): Unit = {
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val uartParams = p(PeripheryUARTKey)
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if (!uartParams.isEmpty) {
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// synchronize uart_rx
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val uart_rx_sync_reg0 = RegInit(true.B)
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uart_rx_sync_reg0 := uart_rx
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val uart_rx_sync_reg1 = RegInit(true.B)
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uart_rx_sync_reg1 := uart_rx_sync_reg0
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// uart connections
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dut.uart(0).rxd := uart_rx_sync_reg1
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uart_tx := dut.uart(0).txd
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}
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}
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//-----------------------------------------------------------------------
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// SPI
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//-----------------------------------------------------------------------
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def connectSPI(dut: HasPeripherySPIModuleImp): Unit = {
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// SPI
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sd_spi_sck := dut.spi(0).sck
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sd_spi_cs := dut.spi(0).cs(0)
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dut.spi(0).dq.zipWithIndex.foreach {
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case(pin, idx) =>
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sd_spi_dq_o(idx) := pin.o
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pin.i := sd_spi_dq_i(idx)
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}
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//-------------------------------------------------------------------
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// SDIO <> SPI Bridge
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//-------------------------------------------------------------------
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val ip_sdio_spi = Module(new sdio_spi_bridge())
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ip_sdio_spi.io.clk := dut_clock
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ip_sdio_spi.io.reset := dut_reset
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// SDIO
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attach(sdio_dat, ip_sdio_spi.io.sd_dat)
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attach(sdio_cmd, ip_sdio_spi.io.sd_cmd)
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sdio_clk := ip_sdio_spi.io.spi_sck
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// SPI
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ip_sdio_spi.io.spi_sck := sd_spi_sck
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ip_sdio_spi.io.spi_cs := sd_spi_cs
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sd_spi_dq_i := ip_sdio_spi.io.spi_dq_i.toBools
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ip_sdio_spi.io.spi_dq_o := sd_spi_dq_o.asUInt
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}
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//---------------------------------------------------------------------
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// MIG
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//---------------------------------------------------------------------
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def connectMIG(dut: HasMemoryXilinxVC707MIGModuleImp): Unit = {
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// Clock & Reset
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dut.xilinxvc707mig.sys_clk_i := sys_clock.asUInt
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mig_clock := dut.xilinxvc707mig.ui_clk
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mig_sys_reset := dut.xilinxvc707mig.ui_clk_sync_rst
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mig_mmcm_locked := dut.xilinxvc707mig.mmcm_locked
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dut.xilinxvc707mig.aresetn := mig_resetn
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dut.xilinxvc707mig.sys_rst := sys_reset
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// Outputs
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ddr3_addr := dut.xilinxvc707mig.ddr3_addr
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ddr3_ba := dut.xilinxvc707mig.ddr3_ba
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ddr3_ras_n := dut.xilinxvc707mig.ddr3_ras_n
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ddr3_cas_n := dut.xilinxvc707mig.ddr3_cas_n
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ddr3_we_n := dut.xilinxvc707mig.ddr3_we_n
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ddr3_reset_n := dut.xilinxvc707mig.ddr3_reset_n
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ddr3_ck_p := dut.xilinxvc707mig.ddr3_ck_p
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ddr3_ck_n := dut.xilinxvc707mig.ddr3_ck_n
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ddr3_cke := dut.xilinxvc707mig.ddr3_cke
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ddr3_cs_n := dut.xilinxvc707mig.ddr3_cs_n
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ddr3_dm := dut.xilinxvc707mig.ddr3_dm
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ddr3_odt := dut.xilinxvc707mig.ddr3_odt
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attach(ddr3_dq, dut.xilinxvc707mig.ddr3_dq)
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attach(ddr3_dqs_n, dut.xilinxvc707mig.ddr3_dqs_n)
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attach(ddr3_dqs_p, dut.xilinxvc707mig.ddr3_dqs_p)
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}
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//---------------------------------------------------------------------
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// PCIE
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//---------------------------------------------------------------------
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def connectPCIe(dut: HasSystemXilinxVC707PCIeX1ModuleImp): Unit = {
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// Clock & Reset
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dut.xilinxvc707pcie.axi_aresetn := pcie_dat_resetn
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pcie_dat_clock := dut.xilinxvc707pcie.axi_aclk_out
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pcie_cfg_clock := dut.xilinxvc707pcie.axi_ctl_aclk_out
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mmcm_lock_pcie := dut.xilinxvc707pcie.mmcm_lock
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dut.xilinxvc707pcie.axi_ctl_aresetn := pcie_dat_resetn
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dut.xilinxvc707pcie.REFCLK_rxp := pci_exp_refclk_rxp
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dut.xilinxvc707pcie.REFCLK_rxn := pci_exp_refclk_rxn
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// PCIeX1 connections
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pci_exp_txp := dut.xilinxvc707pcie.pci_exp_txp
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pci_exp_txn := dut.xilinxvc707pcie.pci_exp_txn
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dut.xilinxvc707pcie.pci_exp_rxp := pci_exp_rxp
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dut.xilinxvc707pcie.pci_exp_rxn := pci_exp_rxn
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}
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}
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