riscv/fpga-shells
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Support both 4G and 1GB DIMM configuration for VC707

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Generate IP TCL and MIG projects from the Chisel blackboxes
This commit is contained in:
Henry Styles
2017-08-21 17:30:01 -07:00
parent e49f49686d
commit 9f75e6eb59
12 changed files with 630 additions and 377 deletions
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xilinx/Makefile
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@ -14,7 +14,7 @@ init = $(FPGA_BUILD_DIR)/.init
$(init): $(fpga_common_script_dir)/init.tcl
mkdir -p $(FPGA_BUILD_DIR) && \
cd $(FPGA_BUILD_DIR) && \
VSRCS="$(VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source $<
VSRCS="$(VSRCS)" IPVIVADOTCLS="$(IPVIVADOTCLS)" $(VIVADO) $(VIVADOFLAGS) -source $<
.PHONY: init
init: $(init)