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TransferSizes: just because a device CAN do more does not mean it should (#15)

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Capping TransferSizes at 128 fits nicely in 3 size bits.
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Wesley W. Terpstra 2017-12-10 00:42:11 -08:00 committed by GitHub
parent ba7beb676d
commit 8b0d7ec91a
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2 changed files with 4 additions and 4 deletions
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4
src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
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@ -38,8 +38,8 @@ class XilinxVC707MIGIsland(c : XilinxVC707MIGParams)(implicit p: Parameters) ext
resources = device.reg,
regionType = RegionType.UNCACHED,
executable = true,
supportsWrite = TransferSizes(1, 256*8),
supportsRead = TransferSizes(1, 256*8))),
supportsWrite = TransferSizes(1, 128),
supportsRead = TransferSizes(1, 128))),
beatBytes = 8)))
lazy val module = new LazyModuleImp(this) {

4
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
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@ -196,8 +196,8 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
address = List(AddressSet(0x60000000L, 0x1fffffffL)),
resources = Seq(Resource(device, "ranges")),
executable = true,
supportsWrite = TransferSizes(1, 256),
supportsRead = TransferSizes(1, 256))),
supportsWrite = TransferSizes(1, 128),
supportsRead = TransferSizes(1, 128))),
beatBytes = 8)))
val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(