TransferSizes: just because a device CAN do more does not mean it should (#15)

Capping TransferSizes at 128 fits nicely in 3 size bits.
2017-12-10 00:42:11 -08:00
parent ba7beb676d
commit 8b0d7ec91a
2 changed files with 4 additions and 4 deletions
--- a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
@@ -38,8 +38,8 @@ class XilinxVC707MIGIsland(c : XilinxVC707MIGParams)(implicit p: Parameters) ext
      resources     = device.reg,
      regionType    = RegionType.UNCACHED,
      executable    = true,
-      supportsWrite = TransferSizes(1, 256*8),
-      supportsRead  = TransferSizes(1, 256*8))),
+      supportsWrite = TransferSizes(1, 128),
+      supportsRead  = TransferSizes(1, 128))),
    beatBytes = 8)))

  lazy val module = new LazyModuleImp(this) {